Release 7.1i Map H.38Xilinx Mapping Report File for Design 'dianti'Design Information------------------Command Line   : C:/Xilinx/bin/nt/map.exe -ise d:\df\df.ise -intstyle ise -p
xcv100-pq240-4 -cm area -pr b -k 4 -c 100 -tx off -o dianti_map.ncd dianti.ngd
dianti.pcf Target Device  : xcv100Target Package : pq240Target Speed   : -4Mapper Version : virtex -- $Revision: 1.26.6.3 $Mapped Date    : Thu Jan 10 20:19:32 2008Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:        32 out of  2,400    1%  Number of 4 input LUTs:           280 out of  2,400   11%Logic Distribution:    Number of occupied Slices:                         149 out of  1,200   12%    Number of Slices containing only related logic:    149 out of    149  100%    Number of Slices containing unrelated logic:         0 out of    149    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          285 out of  2,400   11%      Number used as logic:                       280      Number used as a route-thru:                  5   Number of bonded IOBs:            16 out of    166    9%      IOB Flip Flops:                               3   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  2,008Additional JTAG gate count for IOBs:  816Peak Memory Usage:  97 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------   2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || A                                  | IOB     | INPUT     | LVTTL       |          |      |          |          |       || B                                  | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor1                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor2                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor3                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor4                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor5                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || floor6                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || forbid                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || go_down                            | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || go_up                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       || position<0>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || position<1>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || position<2>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || position<3>                        | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || reset                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 17Number of Equivalent Gates for Design = 2,008Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 1IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 3Unbonded IOBs = 0Bonded IOBs = 16XORs = 5CARRY_INITs = 3CARRY_SKIPs = 0CARRY_MUXes = 5Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 64 input LUTs used as Route-Thrus = 54 input LUTs = 280Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 1Slice Flip Flops = 32Slices = 149F6 Muxes = 0F5 Muxes = 6Number of LUT signals with 4 loads = 12Number of LUT signals with 3 loads = 16Number of LUT signals with 2 loads = 34Number of LUT signals with 1 load = 197NGM Average fanout of LUT = 1.85NGM Maximum fanout of LUT = 19NGM Average fanin for LUT = 3.6036Number of LUT symbols = 280