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Started process "HDL Converter".ERROR: No input file specified for the "HDL Converter" process.Please select an input file (ABEL or AHDL) from the property menu.(Right click on the "HDL Converter" process name and select 'Properties')Process "HDL Converter" did not complete due to error(s) reported by internal script.
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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "r4tgft.v"Module <dianti> compiledNo errors in compilationAnalysis of file <"dianti.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <dianti>.	stop = <u>00	up = <u>01	down = <u>10	lock = <u>11Module <dianti> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <dianti>.    Related source file is "r4tgft.v".    Found finite state machine <FSM_0> for signal <state>.    -----------------------------------------------------------------------    | States             | 3                                              |    | Transitions        | 456                                            |    | Inputs             | 46                                             |    | Outputs            | 3                                              |    | Clock              | clk (rising_edge)                              |    | Reset              | reset (negative)                               |    | Reset type         | asynchronous                                   |    | Reset State        | 00                                             |    | Encoding           | automatic                                      |    | Implementation     | LUT                                            |    -----------------------------------------------------------------------    Found 1-bit register for signal <go_up>.    Found 1-bit register for signal <forbid>.    Found 4-bit register for signal <position>.    Found 1-bit register for signal <go_down>.    Found 1-bit 4-to-1 multiplexer for signal <$n0035>.    Found 1-bit 4-to-1 multiplexer for signal <$n0037>.    Found 1-bit 4-to-1 multiplexer for signal <$n0039>.    Found 1-bit 4-to-1 multiplexer for signal <$n0041>.    Found 1-bit 4-to-1 multiplexer for signal <$n0043>.    Found 1-bit 4-to-1 multiplexer for signal <$n0045>.    Found 1-bit 4-to-1 multiplexer for signal <$n0064>.    Found 6-bit adder for signal <$n0069> created at line 106.    Found 4-bit 4-to-1 multiplexer for signal <$n0070>.    Found 4-bit 4-to-1 multiplexer for signal <$n0071>.    Found 4-bit 4-to-1 multiplexer for signal <$n0072>.    Found 5-bit register for signal <request_down_floor>.    Found 6-bit register for signal <request_stop_floor>.    Found 5-bit register for signal <request_up_floor>.    Found 6-bit register for signal <t>.    Summary:	inferred   1 Finite State Machine(s).	inferred  25 D-type flip-flop(s).	inferred   1 Adder/Subtractor(s).	inferred  19 Multiplexer(s).Unit <dianti> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <state[1:2]> with sequential encoding.------------------- State | Encoding------------------- 00    | 00 01    | 01 10    | 10-------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs                             : 1# Adders/Subtractors               : 1 6-bit adder                       : 1# Registers                        : 23 1-bit register                    : 21 4-bit register                    : 1 6-bit register                    : 1# Multiplexers                     : 10 1-bit 4-to-1 multiplexer          : 7 4-bit 4-to-1 multiplexer          : 3==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <dianti> ...WARNING:Xst:1710 - FF/Latch  <position_3> (without init value) has a constant value of 0 in block <dianti>.Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block dianti, actual ratio is 12.FlipFlop position_2 has been replicated 2 time(s)FlipFlop request_stop_floor_0 has been replicated 1 time(s)FlipFlop request_up_floor_0 has been replicated 1 time(s)FlipFlop state_FFd1 has been replicated 1 time(s)=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : v100pq240-4  Number of Slices:                     150  out of   1200    12%   Number of Slice Flip Flops:            35  out of   2400     1%   Number of 4 input LUTs:               284  out of   2400    11%   Number of bonded IOBs:                 17  out of    170    10%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 35    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 16.069ns (Maximum Frequency: 62.232MHz)   Minimum input arrival time before clock: 9.738ns   Maximum output required time after clock: 11.424ns   Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\df/_ngo -uc df.ucf -p xcv100-pq240-4dianti.ngc dianti.ngd Reading NGO file 'D:/df/dianti.ngc' ...Applying constraints in "df.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "dianti.ngd" ...Writing NGDBUILD log file "dianti.bld"...NGDBUILD done.

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Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\df/_ngo -uc df.ucf -p xcv100-pq240-4dianti.ngc dianti.ngd Reading NGO file 'D:/df/dianti.ngc' ...Applying constraints in "df.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "dianti.ngd" ...Writing NGDBUILD log file "dianti.bld"...NGDBUILD done.
Started process "Map".Using target part "v100pq240-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:        32 out of  2,400    1%  Number of 4 input LUTs:           280 out of  2,400   11%Logic Distribution:    Number of occupied Slices:                         149 out of  1,200   12%    Number of Slices containing only related logic:    149 out of    149  100%    Number of Slices containing unrelated logic:         0 out of    149    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          285 out of  2,400   11%      Number used as logic:                       280      Number used as a route-thru:                  5   Number of bonded IOBs:            16 out of    166    9%      IOB Flip Flops:                               3   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  2,008Additional JTAG gate count for IOBs:  816Peak Memory Usage:  97 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Mapping completed.See MAP report file "dianti_map.mrp" for details.

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Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\df/_ngo -uc df.ucf -p xcv100-pq240-4dianti.ngc dianti.ngd Reading NGO file 'D:/df/dianti.ngc' ...Applying constraints in "df.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "dianti.ngd" ...Writing NGDBUILD log file "dianti.bld"...NGDBUILD done.

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Started process "Create Schematic Symbol".Compiling verilog file "r4tgft.v"tdtfi(verilog) completed successfully.



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Started process "View HDL Instantiation Template".Compiling verilog file "r4tgft.v"tdtfi(verilog) completed successfully.


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Started process "Map".Using target part "v100pq240-4".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:        32 out of  2,400    1%  Number of 4 input LUTs:           280 out of  2,400   11%Logic Distribution:    Number of occupied Slices:                         149 out of  1,200   12%    Number of Slices containing only related logic:    149 out of    149  100%    Number of Slices containing unrelated logic:         0 out of    149    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:          285 out of  2,400   11%      Number used as logic:                       280      Number used as a route-thru:                  5   Number of bonded IOBs:            16 out of    166    9%      IOB Flip Flops:                               3   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  2,008Additional JTAG gate count for IOBs:  816Peak Memory Usage:  97 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.