Project Information                  h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/16/2005 19:05:23

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
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programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

pci_top   EPF10K10ATC144-3 10     29     40   0         0  %    385      66 %

User Pins:                 10     29     40 



Project Information                  h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

pci_top@140                       AD0
pci_top@138                       AD1
pci_top@137                       AD2
pci_top@136                       AD3
pci_top@135                       AD4
pci_top@133                       AD5
pci_top@132                       AD6
pci_top@131                       AD7
pci_top@121                       AD8
pci_top@120                       AD9
pci_top@119                       AD10
pci_top@118                       AD11
pci_top@117                       AD12
pci_top@101                       AD13
pci_top@100                       AD14
pci_top@99                        AD15
pci_top@87                        AD16
pci_top@86                        AD17
pci_top@83                        AD18
pci_top@82                        AD19
pci_top@81                        AD20
pci_top@80                        AD21
pci_top@79                        AD22
pci_top@78                        AD23
pci_top@70                        AD24
pci_top@69                        AD25
pci_top@68                        AD26
pci_top@67                        AD27
pci_top@65                        AD28
pci_top@64                        AD29
pci_top@63                        AD30
pci_top@62                        AD31
pci_top@33                        ALE
pci_top@21                        AL0
pci_top@20                        AL1
pci_top@19                        AL2
pci_top@18                        AL3
pci_top@17                        AL4
pci_top@13                        AL5
pci_top@12                        AL6
pci_top@10                        AL7
pci_top@130                       CBE_0
pci_top@98                        CBE_1
pci_top@88                        CBE_2
pci_top@72                        CBE_3
pci_top@55                        CLK
pci_top@128                       CS_LED
pci_top@122                       CS_SW
pci_top@92                        DEVSEL_
pci_top@89                        FRAME_
pci_top@73                        IDSEL
pci_top@51                        INTA_
pci_top@36                        IoRD_
pci_top@37                        IoWR_
pci_top@90                        IRDY_
pci_top@22                        LocalInt_
pci_top@7                         LocalReset_
pci_top@97                        PAR
pci_top@49                        P00
pci_top@48                        P01
pci_top@47                        P02
pci_top@46                        P03
pci_top@44                        P04
pci_top@43                        P05
pci_top@42                        P06
pci_top@41                        P07
pci_top@32                        P20
pci_top@31                        P21
pci_top@30                        P22
pci_top@29                        P23
pci_top@28                        P24
pci_top@27                        P25
pci_top@26                        P26
pci_top@23                        P27
pci_top@38                        RD_
pci_top@54                        RESET_
pci_top@95                        STOP_
pci_top@91                        TRDY_
pci_top@39                        WR_


Project Information                  h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt

** FILE HIERARCHY **



|pcicore:pci_core1|
|pcicore:pci_core1|lpm_add_sub:2596|
|pcicore:pci_core1|lpm_add_sub:2596|addcore:adder2|
|pcicore:pci_core1|lpm_add_sub:2596|addcore:adder1|
|pcicore:pci_core1|lpm_add_sub:2596|addcore:adder0|
|pcicore:pci_core1|lpm_add_sub:2596|look_add:look_aheader|
|pcicore:pci_core1|lpm_add_sub:2596|altshift:result_ext_latency_ffs|
|pcicore:pci_core1|lpm_add_sub:2596|altshift:carry_ext_latency_ffs|
|pcicore:pci_core1|lpm_add_sub:2596|altshift:oflow_ext_latency_ffs|
|pcicore:pci_core1|lpm_xor:2597|
|pcicore:pci_core1|lpm_xor:2598|
|pcicore:pci_core1|lpm_xor:2599|
|pcicore:pci_core1|lpm_xor:2600|
|pcicore:pci_core1|lpm_xor:2601|


Device-Specific Information:         h:\mydesign\ifspci\pub\pci_ip\pci_top.rpt
pci_top

***** Logic for device 'pci_top' compiled without errors.




Device: EPF10K10ATC144-3

FLEX 10K Configuration Scheme: Passive Parallel Asynchronous

Device Options: