library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity dram_control is
  port(clk:in std_logic;
      addr:in std_logic_vector(31 downto 0);
       ads:in std_logic;
read_write:in std_logic;
     reset:in std_logic;
       ack:out std_logic;
        we:out std_logic;
     ready:out std_logic;
      dram:out std_logic_vector(9 downto 0);
       ras:out std_logic_vector(1 downto 0);
       cas:out std_logic_vector(3 downto 0));
end;

architecture one of dram_control is
type state is(idle,address_detect,row_address,ras_assert,col_address,cas_assert,
              data_ready,wait_state,refresh0,refresh1);
signal present_state,next_state:state;
signal stroed:std_logic_vector(31 downto 0);
signal ref_timer:std_logic_vector(8 downto 0);
signal ref_request:std_logic;
signal match,readr:std_logic;
signal ack_tmp,we_tmp,ready_tmp:std_logic;
signal dram_tmp:std_logic_vector(9 downto 0);
signal ras_tmp:std_logic_vector(1 downto 0);
signal cas_tmp:std_logic_vector(3 downto 0);
alias row_addr:std_logic_vector(9 downto 0) is stroed(19 downto 10);
alias col_addr:std_logic_vector(9 downto 0) is stroed(9 downto 0);
begin

process(reset,clk)
begin
if reset='1' then
stroed<=(others=>'0'); readr<='0';
elsif clk'event and clk='1' then
  if ads='0' then
  stroed<=addr; readr<=read_write;
  end if;
end if;
end process;

match<='1' when stroed(31 downto 21)="00000000000" else
       '0';

process(row_addr,col_addr,present_state)
begin
if present_state=row_address or present_state=ras_assert then
dram_tmp<=row_addr;
else dram_tmp<=col_addr;
end if;
end process;

process(reset,clk)
begin
if reset='1' then
ref_timer<=(others=>'0');
elsif clk'event and clk='1' then
  if ref_timer="100111000" then
  ref_timer<=(others=>'0');
  else ref_timer<=ref_timer+1;
  end if;
end if;
end process;

ref_request<='1' when (ref_timer="100111000" or (ref_request='1' and present_state/=refresh0)) else
             '0';

process(present_state,ref_request,ads,match)
begin
case present_state is
when idle=>
  if ref_request='1' then
  next_state<=refresh0;
  elsif ads='0' then
  next_state<=address_detect;
  else next_state<=idle;
  end if;
when address_detect=>
  if match='1' then
  next_state<=row_address;
  else next_state<=idle;
  end if;
when row_address=>next_state<=ras_assert;
when ras_assert=>next_state<=col_address;
when col_address=>next_state<=cas_assert;
when cas_assert=>next_state<=data_ready;
when data_ready=>next_state<=wait_state;
when wait_state=>next_state<=idle;
when refresh0=>next_state<=refresh1;
when refresh1=>next_state<=idle;
end case;
end process;

process(reset,clk)
begin
if reset='1' then
present_state<=idle;
elsif clk'event and clk='1' then
present_state<=next_state;
end if;
end process;

with present_state select
cas_tmp<="0000" when cas_assert|data_ready|wait_state|refresh0|refresh1,
         "1111" when others;

ras_tmp<="00" when (present_state=refresh1) else
         "01" when (stroed(20)='1' and (present_state=ras_assert or present_state=col_address or
                present_state=cas_assert or present_state=data_ready or present_state=wait_state)) else
         "10" when (stroed(20)='0' and (present_state=ras_assert or present_state=col_address or
                present_state=cas_assert or present_state=data_ready or present_state=wait_state)) else 
         "11";

we_tmp<='0' when (readr='0' and (present_state=col_address or present_state=cas_assert or 
              present_state=data_ready)) else
        '1';

ack_tmp<='0' when (present_state=address_detect and match='1') else
         '1';

ready_tmp<='0' when (readr='1' and (present_state=data_ready or present_state=wait_state)) else
           '1';

process(reset,clk)
begin
if reset='1' then
ack<='1'; we<='1'; ready<='1';
dram<=(others=>'0'); cas<="1111"; ras<="11";
elsif clk'event and clk='1' then
ack<=ack_tmp; we<=we_tmp; ready<=ready_tmp;
cas<=cas_tmp; ras<=ras_tmp; dram<=dram_tmp;
end if;
end process;

end;