{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_18_is_x cpu_0_test_bench.v(104) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(104): object \"A_wr_data_unfiltered_18_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 104 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_19_is_x cpu_0_test_bench.v(105) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(105): object \"A_wr_data_unfiltered_19_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 105 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_1_is_x cpu_0_test_bench.v(106) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(106): object \"A_wr_data_unfiltered_1_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 106 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_20_is_x cpu_0_test_bench.v(107) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(107): object \"A_wr_data_unfiltered_20_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 107 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_21_is_x cpu_0_test_bench.v(108) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(108): object \"A_wr_data_unfiltered_21_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 108 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_22_is_x cpu_0_test_bench.v(109) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(109): object \"A_wr_data_unfiltered_22_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 109 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_23_is_x cpu_0_test_bench.v(110) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(110): object \"A_wr_data_unfiltered_23_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 110 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_24_is_x cpu_0_test_bench.v(111) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(111): object \"A_wr_data_unfiltered_24_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 111 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_25_is_x cpu_0_test_bench.v(112) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(112): object \"A_wr_data_unfiltered_25_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 112 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_26_is_x cpu_0_test_bench.v(113) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(113): object \"A_wr_data_unfiltered_26_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 113 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_27_is_x cpu_0_test_bench.v(114) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(114): object \"A_wr_data_unfiltered_27_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 114 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_28_is_x cpu_0_test_bench.v(115) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(115): object \"A_wr_data_unfiltered_28_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 115 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_29_is_x cpu_0_test_bench.v(116) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(116): object \"A_wr_data_unfiltered_29_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 116 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_2_is_x cpu_0_test_bench.v(117) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(117): object \"A_wr_data_unfiltered_2_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 117 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_30_is_x cpu_0_test_bench.v(118) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(118): object \"A_wr_data_unfiltered_30_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 118 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_31_is_x cpu_0_test_bench.v(119) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(119): object \"A_wr_data_unfiltered_31_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 119 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_3_is_x cpu_0_test_bench.v(120) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(120): object \"A_wr_data_unfiltered_3_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 120 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_4_is_x cpu_0_test_bench.v(121) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(121): object \"A_wr_data_unfiltered_4_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 121 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_5_is_x cpu_0_test_bench.v(122) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(122): object \"A_wr_data_unfiltered_5_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 122 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_6_is_x cpu_0_test_bench.v(123) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(123): object \"A_wr_data_unfiltered_6_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 123 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_7_is_x cpu_0_test_bench.v(124) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(124): object \"A_wr_data_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 124 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_8_is_x cpu_0_test_bench.v(125) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(125): object \"A_wr_data_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 125 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "A_wr_data_unfiltered_9_is_x cpu_0_test_bench.v(126) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(126): object \"A_wr_data_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 126 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_inst cpu_0_test_bench.v(129) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(129): object \"W_inst\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 129 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_vinst cpu_0_test_bench.v(258) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(258): object \"W_vinst\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 258 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 cpu_0_test_bench.v(262) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(262): truncated value with size 32 to match size of target (24)" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 262 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 cpu_0_test_bench.v(271) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(271): truncated value with size 32 to match size of target (24)" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 271 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 cpu_0_test_bench.v(289) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(289): truncated value with size 32 to match size of target (24)" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0_test_bench.v" 289 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_ic_data_module SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data " "Info: Elaborating entity \"cpu_0_ic_data_module\" for hierarchy \"SmartSOPC_Flash_Programmer:inst\|cpu_0:the_cpu_0\|cpu_0_ic_data_module:cpu_0_ic_data\"" {  } { { "cpu_0.v" "cpu_0_ic_data" { Text "C:/altera/kits/nios2/examples/SmartSOPC_Flash_Programmer/system/cpu_0.v" 2951 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES