Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
32
1637
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
SmartSOPC_Flash_Programmer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SmartSOPC_Flash_Programmer.v
1146296568
7
# storage
db|SmartSOPC_Flash_Programmer.(1).cnf
db|SmartSOPC_Flash_Programmer.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst
}
# end
# entity
asmi_asmi_control_port_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SmartSOPC_Flash_Programmer.v
1146296568
7
# storage
db|SmartSOPC_Flash_Programmer.(2).cnf
db|SmartSOPC_Flash_Programmer.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port
}
# end
# entity
asmi
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1146296552
7
# storage
db|SmartSOPC_Flash_Programmer.(3).cnf
db|SmartSOPC_Flash_Programmer.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|asmi:the_asmi
}
# end
# entity
asmi_sub
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1146296552
7
# storage
db|SmartSOPC_Flash_Programmer.(4).cnf
db|SmartSOPC_Flash_Programmer.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|asmi:the_asmi|asmi_sub:the_asmi_sub
}
# end
# entity
tornado_asmi_atom
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
asmi.v
1146296552
7
# storage
db|SmartSOPC_Flash_Programmer.(5).cnf
db|SmartSOPC_Flash_Programmer.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom
}
# end
# entity
cpu_0_data_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SmartSOPC_Flash_Programmer.v
1146296568
7
# storage
db|SmartSOPC_Flash_Programmer.(6).cnf
db|SmartSOPC_Flash_Programmer.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# end
# entity
cpu_0_instruction_master_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SmartSOPC_Flash_Programmer.v
1146296568
7
# storage
db|SmartSOPC_Flash_Programmer.(7).cnf
db|SmartSOPC_Flash_Programmer.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# end
# entity
cpu_0
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1146296542
7
# storage
db|SmartSOPC_Flash_Programmer.(8).cnf
db|SmartSOPC_Flash_Programmer.(8).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0
}
# end
# entity
cpu_0_test_bench
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
1146296538
7
# storage
db|SmartSOPC_Flash_Programmer.(9).cnf
db|SmartSOPC_Flash_Programmer.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# end
# entity
cpu_0_ic_data_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1146296542
7
# storage
db|SmartSOPC_Flash_Programmer.(10).cnf
db|SmartSOPC_Flash_Programmer.(10).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SmartSOPC_Flash_Programmer.(11).cnf
db|SmartSOPC_Flash_Programmer.(11).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_2d21
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
..|..|..|..|..|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
}
# end
# entity
cpu_0_ic_tag_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1146296542
7
# storage
db|SmartSOPC_Flash_Programmer.(13).cnf
db|SmartSOPC_Flash_Programmer.(13).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
ic_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SmartSOPC_Flash_Programmer.(14).cnf
db|SmartSOPC_Flash_Programmer.(14).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
23
PARAMETER_DEC
USR
WIDTHAD_A
4
PARAMETER_DEC
USR
NUMWORDS_A
16
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
23
PARAMETER_DEC
USR
WIDTHAD_B
4
PARAMETER_DEC
USR
NUMWORDS_B
16
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN