INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_gd41
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
..|..|..|..|..|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_gd41
# case_insensitive
# source_file
db|altsyncram_gd41.tdf
1146297414
6
# storage
db|SmartSOPC_Flash_Programmer.(21).cnf
db|SmartSOPC_Flash_Programmer.(21).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
q_b16
q_b17
q_b18
q_b19
q_b20
q_b21
q_b22
q_b23
q_b24
q_b25
q_b26
q_b27
q_b28
q_b29
q_b30
q_b31
}
# memory_file {
rf_ram_a.mif
1146296534
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_gd41:auto_generated
}
# end
# entity
cpu_0_register_bank_b_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
1146296542
7
# storage
db|SmartSOPC_Flash_Programmer.(22).cnf
db|SmartSOPC_Flash_Programmer.(22).cnf
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
rf_ram_b.mif
PARAMETER_STRING
USR
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|SmartSOPC_Flash_Programmer.(23).cnf
db|SmartSOPC_Flash_Programmer.(23).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hd41
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
..|..|..|..|..|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
SmartSOPC_Flash_Programmer:inst|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_hd41
# case_insensitive
# source_file
db|altsyncram_hd41.tdf
1146297416
6
# storage
db|SmartSOPC_Flash_Programmer.(24).cnf
db|SmartSOPC_Flash_Programmer.(24).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
data_a16
data_a17
data_a18
data_a19
data_a20
data_a21
data_a22
data_a23
data_a24
data_a25
data_a26
data_a27
data_a28
data_a29
data_a30
data_a31
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
clocken1
q_b0
q_b1
q_b2
q_b3
q_b4