data_to_cpu[8] <= data_to_cpu[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[9] <= data_to_cpu[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[10] <= data_to_cpu[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[11] <= data_to_cpu[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[12] <= data_to_cpu[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[13] <= data_to_cpu[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[14] <= data_to_cpu[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_to_cpu[15] <= data_to_cpu[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataavailable <= RRDY.DB_MAX_OUTPUT_PORT_TYPE
endofpacket <= EOP.DB_MAX_OUTPUT_PORT_TYPE
irq <= irq_reg.DB_MAX_OUTPUT_PORT_TYPE
readyfordata <= TRDY~0.DB_MAX_OUTPUT_PORT_TYPE


|SmartSOPC_Flash_Programmer_top|SmartSOPC_Flash_Programmer:inst|asmi:the_asmi|tornado_asmi_atom:the_tornado_asmi_atom
dclkin => the_tornado_spiblock.CLK
oe => the_tornado_spiblock.OE
scein => the_tornado_spiblock.SCEIN
sdoin => the_tornado_spiblock.SDOIN
data0out <= the_tornado_spiblock.DATAOUT


|SmartSOPC_Flash_Programmer_top|SmartSOPC_Flash_Programmer:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master
asmi_asmi_control_port_irq_from_sa => cpu_0_data_master_irq[1].DATAIN
asmi_asmi_control_port_readdata_from_sa[0] => cpu_0_data_master_readdata~0.IN0
asmi_asmi_control_port_readdata_from_sa[1] => cpu_0_data_master_readdata~1.IN1
asmi_asmi_control_port_readdata_from_sa[2] => cpu_0_data_master_readdata~2.IN1
asmi_asmi_control_port_readdata_from_sa[3] => cpu_0_data_master_readdata~3.IN1
asmi_asmi_control_port_readdata_from_sa[4] => cpu_0_data_master_readdata~4.IN1
asmi_asmi_control_port_readdata_from_sa[5] => cpu_0_data_master_readdata~5.IN1
asmi_asmi_control_port_readdata_from_sa[6] => cpu_0_data_master_readdata~6.IN1
asmi_asmi_control_port_readdata_from_sa[7] => cpu_0_data_master_readdata~7.IN1
asmi_asmi_control_port_readdata_from_sa[8] => cpu_0_data_master_readdata~8.IN1
asmi_asmi_control_port_readdata_from_sa[9] => cpu_0_data_master_readdata~9.IN1
asmi_asmi_control_port_readdata_from_sa[10] => cpu_0_data_master_readdata~10.IN1
asmi_asmi_control_port_readdata_from_sa[11] => cpu_0_data_master_readdata~11.IN1
asmi_asmi_control_port_readdata_from_sa[12] => cpu_0_data_master_readdata~12.IN1
asmi_asmi_control_port_readdata_from_sa[13] => cpu_0_data_master_readdata~13.IN1
asmi_asmi_control_port_readdata_from_sa[14] => cpu_0_data_master_readdata~14.IN1
asmi_asmi_control_port_readdata_from_sa[15] => cpu_0_data_master_readdata~15.IN1
cfi_flash_0_s1_wait_counter_eq_0 => pre_dbs_count_enable~12.IN0
cfi_flash_0_s1_wait_counter_eq_1 => r_1~28.IN1
clk => registered_cpu_0_data_master_readdata[31].CLK
clk => registered_cpu_0_data_master_readdata[30].CLK
clk => registered_cpu_0_data_master_readdata[29].CLK
clk => registered_cpu_0_data_master_readdata[28].CLK
clk => registered_cpu_0_data_master_readdata[27].CLK
clk => registered_cpu_0_data_master_readdata[26].CLK
clk => registered_cpu_0_data_master_readdata[25].CLK
clk => registered_cpu_0_data_master_readdata[24].CLK
clk => registered_cpu_0_data_master_readdata[23].CLK
clk => registered_cpu_0_data_master_readdata[22].CLK
clk => registered_cpu_0_data_master_readdata[21].CLK
clk => registered_cpu_0_data_master_readdata[20].CLK
clk => registered_cpu_0_data_master_readdata[19].CLK
clk => registered_cpu_0_data_master_readdata[18].CLK
clk => registered_cpu_0_data_master_readdata[17].CLK
clk => registered_cpu_0_data_master_readdata[16].CLK
clk => registered_cpu_0_data_master_readdata[15].CLK
clk => registered_cpu_0_data_master_readdata[14].CLK
clk => registered_cpu_0_data_master_readdata[13].CLK
clk => registered_cpu_0_data_master_readdata[12].CLK
clk => registered_cpu_0_data_master_readdata[11].CLK
clk => registered_cpu_0_data_master_readdata[10].CLK
clk => registered_cpu_0_data_master_readdata[9].CLK
clk => registered_cpu_0_data_master_readdata[8].CLK
clk => registered_cpu_0_data_master_readdata[7].CLK
clk => registered_cpu_0_data_master_readdata[6].CLK
clk => registered_cpu_0_data_master_readdata[5].CLK
clk => registered_cpu_0_data_master_readdata[4].CLK
clk => registered_cpu_0_data_master_readdata[3].CLK
clk => registered_cpu_0_data_master_readdata[2].CLK
clk => registered_cpu_0_data_master_readdata[1].CLK
clk => registered_cpu_0_data_master_readdata[0].CLK
clk => cpu_0_data_master_no_byte_enables_and_last_term~reg0.CLK
clk => dbs_16_reg_segment_0[15].CLK
clk => dbs_16_reg_segment_0[14].CLK
clk => dbs_16_reg_segment_0[13].CLK
clk => dbs_16_reg_segment_0[12].CLK
clk => dbs_16_reg_segment_0[11].CLK
clk => dbs_16_reg_segment_0[10].CLK
clk => dbs_16_reg_segment_0[9].CLK
clk => dbs_16_reg_segment_0[8].CLK
clk => dbs_16_reg_segment_0[7].CLK
clk => dbs_16_reg_segment_0[6].CLK
clk => dbs_16_reg_segment_0[5].CLK
clk => dbs_16_reg_segment_0[4].CLK
clk => dbs_16_reg_segment_0[3].CLK
clk => dbs_16_reg_segment_0[2].CLK
clk => dbs_16_reg_segment_0[1].CLK
clk => dbs_16_reg_segment_0[0].CLK
clk => cpu_0_data_master_dbs_address[1]~reg0.CLK
clk => cpu_0_data_master_dbs_address[0]~reg0.CLK
clk => cpu_0_data_master_waitrequest~reg0.CLK
cpu_0_data_master_address[0] => cpu_0_data_master_address_to_slave[0].DATAIN
cpu_0_data_master_address[1] => cpu_0_data_master_address_to_slave[1].DATAIN
cpu_0_data_master_address[2] => cpu_0_data_master_address_to_slave[2].DATAIN
cpu_0_data_master_address[3] => cpu_0_data_master_address_to_slave[3].DATAIN
cpu_0_data_master_address[4] => cpu_0_data_master_address_to_slave[4].DATAIN
cpu_0_data_master_address[5] => cpu_0_data_master_address_to_slave[5].DATAIN
cpu_0_data_master_address[6] => cpu_0_data_master_address_to_slave[6].DATAIN
cpu_0_data_master_address[7] => cpu_0_data_master_address_to_slave[7].DATAIN
cpu_0_data_master_address[8] => cpu_0_data_master_address_to_slave[8].DATAIN
cpu_0_data_master_address[9] => cpu_0_data_master_address_to_slave[9].DATAIN
cpu_0_data_master_address[10] => cpu_0_data_master_address_to_slave[10].DATAIN
cpu_0_data_master_address[11] => cpu_0_data_master_address_to_slave[11].DATAIN
cpu_0_data_master_address[12] => cpu_0_data_master_address_to_slave[12].DATAIN
cpu_0_data_master_address[13] => cpu_0_data_master_address_to_slave[13].DATAIN
cpu_0_data_master_address[14] => cpu_0_data_master_address_to_slave[14].DATAIN
cpu_0_data_master_address[15] => cpu_0_data_master_address_to_slave[15].DATAIN
cpu_0_data_master_address[16] => cpu_0_data_master_address_to_slave[16].DATAIN
cpu_0_data_master_address[17] => cpu_0_data_master_address_to_slave[17].DATAIN
cpu_0_data_master_address[18] => cpu_0_data_master_address_to_slave[18].DATAIN
cpu_0_data_master_address[19] => cpu_0_data_master_address_to_slave[19].DATAIN
cpu_0_data_master_address[20] => cpu_0_data_master_address_to_slave[20].DATAIN
cpu_0_data_master_address[21] => ~NO_FANOUT~
cpu_0_data_master_address[22] => ~NO_FANOUT~
cpu_0_data_master_address[23] => cpu_0_data_master_address_to_slave[23].DATAIN
cpu_0_data_master_byteenable_cfi_flash_0_s1[0] => reduce_nor~2.IN1
cpu_0_data_master_byteenable_cfi_flash_0_s1[1] => reduce_nor~2.IN0
cpu_0_data_master_byteenable_payload_buffer_s1[0] => reduce_nor~1.IN1
cpu_0_data_master_byteenable_payload_buffer_s1[1] => reduce_nor~1.IN0
cpu_0_data_master_granted_asmi_asmi_control_port => ~NO_FANOUT~
cpu_0_data_master_granted_cfi_flash_0_s1 => r_1~20.IN0
cpu_0_data_master_granted_cfi_flash_0_s1 => pre_dbs_count_enable~11.IN1
cpu_0_data_master_granted_data_RAM_s1 => r_0~8.IN1
cpu_0_data_master_granted_firmware_ROM_s1 => r_0~20.IN1
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~
cpu_0_data_master_granted_payload_buffer_s1 => r_0~45.IN0
cpu_0_data_master_granted_payload_buffer_s1 => pre_dbs_count_enable~4.IN1
cpu_0_data_master_granted_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_qualified_request_asmi_asmi_control_port => r_0~2.IN1
cpu_0_data_master_qualified_request_asmi_asmi_control_port => r_0~0.IN1
cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_1~14.IN0
cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_1~27.IN1
cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_1~22.IN1
cpu_0_data_master_qualified_request_cfi_flash_0_s1 => r_1~20.IN1
cpu_0_data_master_qualified_request_data_RAM_s1 => r_0~5.IN0
cpu_0_data_master_qualified_request_data_RAM_s1 => r_0~14.IN1
cpu_0_data_master_qualified_request_data_RAM_s1 => r_0~10.IN1
cpu_0_data_master_qualified_request_data_RAM_s1 => r_0~8.IN0
cpu_0_data_master_qualified_request_firmware_ROM_s1 => r_0~17.IN0
cpu_0_data_master_qualified_request_firmware_ROM_s1 => r_0~26.IN1
cpu_0_data_master_qualified_request_firmware_ROM_s1 => r_0~22.IN1
cpu_0_data_master_qualified_request_firmware_ROM_s1 => r_0~20.IN0
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_0~29.IN1
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_0~35.IN1
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave => r_0~31.IN1
cpu_0_data_master_qualified_request_payload_buffer_s1 => r_0~39.IN0
cpu_0_data_master_qualified_request_payload_buffer_s1 => r_1~4.IN1
cpu_0_data_master_qualified_request_payload_buffer_s1 => r_1~0.IN1
cpu_0_data_master_qualified_request_payload_buffer_s1 => r_0~45.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~11.IN1
cpu_0_data_master_qualified_request_sysid_control_slave => r_1~8.IN1
cpu_0_data_master_read => r_0~1.IN0
cpu_0_data_master_read => r_0~11.IN0
cpu_0_data_master_read => r_0~23.IN0
cpu_0_data_master_read => r_0~32.IN0
cpu_0_data_master_read => r_1~2.IN0
cpu_0_data_master_read => r_1~9.IN0
cpu_0_data_master_read => r_1~24.IN0
cpu_0_data_master_read => cpu_0_data_master_waitrequest~0.IN1
cpu_0_data_master_read => r_1~22.IN0
cpu_0_data_master_read => r_1~8.IN0
cpu_0_data_master_read => r_1~0.IN0
cpu_0_data_master_read => r_0~31.IN0
cpu_0_data_master_read => r_0~22.IN0
cpu_0_data_master_read => r_0~10.IN0
cpu_0_data_master_read => r_0~0.IN0
cpu_0_data_master_read_data_valid_asmi_asmi_control_port => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_cfi_flash_0_s1 => pre_dbs_count_enable~10.IN0
cpu_0_data_master_read_data_valid_data_RAM_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_firmware_ROM_s1 => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave => ~NO_FANOUT~
cpu_0_data_master_read_data_valid_payload_buffer_s1 => pre_dbs_count_enable~3.IN0
cpu_0_data_master_read_data_valid_sysid_control_slave => ~NO_FANOUT~
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~0.IN1
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~1.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~2.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~3.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~4.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~5.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~6.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~7.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~8.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~9.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~10.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~11.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~12.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~13.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~14.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~15.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~64.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~65.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~66.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~67.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~68.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~69.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~70.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~71.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~72.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~73.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~74.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~75.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~76.IN0
cpu_0_data_master_requests_asmi_asmi_control_port => cpu_0_data_master_readdata~77.IN0