SYSTEM SmartSOPC_Flash_Programmer
{
   System_Wizard_Version = "5.00";
   System_Wizard_Build = "168";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONE";
      clock_freq = "80000000";
      generate_hdl = "1";
      generate_sdk = "0";
      do_build_sim = "0";
      hdl_language = "verilog";
      view_master_columns = "1";
      view_master_priorities = "0";
      board_class = "";
      name_column_width = "66";
      desc_column_width = "66";
      bustype_column_width = "0";
      base_column_width = "68";
      end_column_width = "68";
      view_frame_window = "91:55:654:778";
      do_log_history = "0";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
         altera_avalon_epcs_flash_controller 
         {
            reference_designators = "U10";
         }
      }
      CLOCKS 
      {
         clk = "80000000";
      }
      device_family_id = "CYCLONE";
      hardcopy_compatible = "0";
      clock_column_width = "66";
   }
   MODULE cpu_0
   {
      class = "altera_nios2";
      class_version = "5.0";
      iss_model_name = "altera_nios2";
      HDL_INFO 
      {
         PLI_Files = "";
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0.v";
         Synthesis_Only_Files = "";
      }
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT i_address
            {
               direction = "output";
               type = "address";
               width = "24";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               direction = "output";
               type = "read";
               width = "1";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               Is_Enabled = "1";
               direction = "input";
               type = "readdatavalid";
               width = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Linewrap_Bursts = "";
            Interleave_Bursts = "";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
         }
      }
      MASTER data_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               direction = "output";
               type = "address";
               width = "24";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               direction = "output";
               type = "byteenable";
               width = "4";
               Is_Enabled = "1";
            }
            PORT d_irq
            {
               direction = "input";
               type = "irq";
               width = "32";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               direction = "output";
               type = "read";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               direction = "input";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               direction = "input";
               type = "waitrequest";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               direction = "output";
               type = "write";
               width = "1";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               direction = "output";
               type = "writedata";
               width = "32";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-31";
            Is_Enabled = "1";
            Maximum_Burst_Size = "1";
            Burst_On_Burst_Boundaries_Only = "";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      SLAVE jtag_debug_module
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Address_Width = "9";
            Accepts_Internal_Connections = "1";
            Requires_Internal_Connections = "instruction_master,data_master";
            Accepts_External_Connections = "0";
            Is_Enabled = "0";
            Address_Alignment = "dynamic";
            Base_Address = "";
            Is_Memory_Device = "1";
            Is_Printable_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Has_IRQ = "0";
            JTAG_Hub_Base_Id = "1118278";
            JTAG_Hub_Instance_Id = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         asp_debug = "0";
         asp_core_debug = "0";
         CPU_Architecture = "nios2";
         do_generate = "1";
         cpu_selection = "f";
         CPU_Implementation = "fast";
         cache_has_dcache = "0";
         cache_has_icache = "1";
         cache_dcache_size = "0";
         cache_icache_size = "512";
         include_debug = "0";
         include_trace = "0";
         include_oci = "0";
         debug_level = "1";
         oci_offchip_trace = "0";
         oci_onchip_trace = "0";
         oci_data_trace = "0";
         oci_trace_addr_width = "7";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_num_pm = "0";
         oci_pm_width = "40";
         oci_debugreq_signals = "0";
         oci_instance_number = "1";
         hardware_multiply_present = "0";
         hardware_divide_present = "0";
         bht_ptr_sz = "8";
         reset_slave = "firmware_ROM/s1";
         reset_offset = "0x0";
         exc_slave = "firmware_ROM/s1";
         exc_offset = "0x00000020";
         break_slave = "firmware_ROM/s1";
         break_offset = "0x0";
         break_slave_override = "";
         break_offset_override = "0x20";
         legacy_sdk_support = "0";
         altera_internal_test = "0";
         full_waveform_signals = "0";
         activate_model_checker = "0";
         activate_monitors_and_trace = "0";
         bit_31_bypass_dcache = "1";
         always_bypass_dcache = "0";
         always_encrypt = "1";
         hdl_sim_caches_cleared = "1";
         allow_full_address_range = "0";
         consistent_synthesis = "0";
         ibuf_ptr_sz = "4";
         jtb_ptr_sz = "5";
         performance_counters_present = "0";
         performance_counters_width = "32";
         ras_ptr_sz = "4";
         inst_decode_in_submodule = "0";
         register_dependency_in_submodule = "0";
         source_operands_in_submodule = "0";
         alu_in_submodule = "0";
         stdata_in_submodule = "0";
         shift_rot_2N_in_submodule = "0";
         control_regs_in_submodule = "0";
         mult_cell_in_submodule = "0";
         M_inst_result_mux_in_submodule = "0";
         dcache_load_aligner_in_submodule = "0";
         hardware_divide_in_submodule = "0";
         mult_result_mux_in_submodule = "0";
         shift_rotate_in_submodule = "0";
         register_file_write_data_mux_in_submodule = "0";
         avalon_imaster_in_submodule = "0";
         avalon_dmaster_in_submodule = "0";
         avalon_load_aligner_in_submodule = "0";
         hbreak_test = "0";
         iss_trace_on = "0";
         iss_trace_warning = "1";
         iss_trace_info = "1";
         iss_trace_disassembly = "0";
         iss_trace_registers = "0";
         iss_trace_instr_count = "0";
         iss_software_debug = "0";
         iss_software_debug_port = "9996";
         iss_memory_dump_start = "";
         iss_memory_dump_end = "";
         Boot_Copier = "boot_loader_cfi.srec";
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
         CONSTANTS 
         {
            CONSTANT __nios_catch_irqs__
            {
               value = "1";
               comment = "Include panic handler for all irqs (needs uart)";
            }
            CONSTANT __nios_use_constructors__
            {
               value = "1";
               comment = "Call c++ static constructors";
            }
            CONSTANT __nios_use_small_printf__
            {
               value = "1";
               comment = "Smaller non-ANSI printf, with no floating point";
            }
            CONSTANT nasys_has_icache
            {
               value = "1";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_icache_size
            {
               value = "512";
               comment = "Size in bytes of instruction cache";
            }
            CONSTANT nasys_icache_line_size
            {
               value = "32";
               comment = "Size in bytes of each icache line";
            }
            CONSTANT nasys_icache_line_size_log2
            {
               value = "5";
               comment = "Log2 size in bytes of each icache line";
            }
            CONSTANT nasys_has_dcache
            {
               value = "0";
               comment = "True if instruction cache present";
            }
            CONSTANT nasys_dcache_size
            {
               value = "0";
               comment = "Size in bytes of data cache";
            }
            CONSTANT nasys_dcache_line_size
            {
               value = "4";
               comment = "Size in bytes of each dcache line";
            }
            CONSTANT nasys_dcache_line_size_log2
            {
               value = "2";
               comment = "Log2 size in bytes of each dcache line";
            }
         }
         mainmem_slave = "";
         datamem_slave = "";
         maincomm_slave = "";
         debugcomm_slave = "";
         germs_monitor_id = "";
         remove_hardware_multiplier = "0";
         activate_trace = "1";
         activate_monitors = "1";
         activate_test_end_checker = "0";
         clear_x_bits_ld_non_bypass = "1";
         gui_include_avalon_instruction_master = "1";
         gui_include_avalon_data_master = "1";
         gui_include_dcache = "1";
         gui_include_tightly_coupled_instruction_masters = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "1";
         num_tightly_coupled_instruction_masters = "0";
         num_tightly_coupled_data_masters = "0";
         cache_dcache_line_size = "4";
         cache_icache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_icache_burst_type = "none";
         include_third_party_debug_port = "0";
         oci_trigger_arming = "1";
         gui_hardware_multiply_setting = "no_mul_small_le_shift";
         hardware_multiply_uses_les = "0";
         hardware_multiply_omits_msw = "1";
         hardware_multiply_impl = "no_mul";
         altera_show_unreleased_features = "0";
         illegal_instructions_trap = "0";
         gui_branch_prediction_type = "Automatic";
         branch_prediction_type = "Dynamic";
         bht_index_pc_only = "0";
         shift_rot_impl = "small_le_shift";
         mmu_present = "0";
         process_id_num_bits = "10";
         dtlb_ptr_sz = "7";
         dtlb_num_ways = "4";
         udtlb_num_entries = "6";
         itlb_ptr_sz = "7";
         itlb_num_ways = "4";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x00000000";
         cache_omit_dcache = "0";
         cache_omit_icache = "0";
         omit_instruction_master = "0";
         omit_data_master = "0";
         license_status = "encrypted";
         gui_num_tightly_coupled_instruction_masters = "1";
         gui_omit_avalon_data_master = "0";
         cache_dcache_ram_block_type = "AUTO";
         cache_icache_ram_block_type = "AUTO";
         oci_embedded_pll = "1";
         gui_hardware_divide_setting = "0";
         cpuid_sz = "1";
         cpuid_value = "0";
      }
      SYSTEM_BUILDER_INFO 
      {
         Parameters_Signature = "";
         Is_CPU = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "STRATIX,STRATIXII,CYCLONE,CYCLONEII";
         Default_Module_Name = "cpu";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
            Settings_Summary = "Nios II/f