?? smartsopc_flash_programmer.ptf
字號(hào):
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
PORT_WIRING
{
}
}
MODULE data_RAM
{
class = "altera_avalon_onchip_memory2";
class_version = "5.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/data_RAM.v";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "1";
Size_Multiple = "1024";
contents_info = "QUARTUS_PROJECT_DIR/data_RAM.hex 1146296544 ";
MAKE
{
TARGET delete_placeholder_warning
{
data_RAM
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
data_RAM
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x00010000 0x103FF --width=32 $(QUARTUS_PROJECT_DIR)/data_RAM.hex --create-lanes=0";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/data_RAM.hex";
}
}
TARGET sim
{
data_RAM
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "8";
Is_Enabled = "1";
}
PORT byteenable
{
direction = "input";
type = "byteenable";
width = "4";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT clken
{
Is_Enabled = "1";
default_value = "1'b1";
direction = "input";
type = "clken";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "8";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "1024";
Read_Latency = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00010000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
Is_Channel = "1";
Is_Writable = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "8";
Data_Width = "32";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "1024";
Read_Latency = "1";
Is_Enabled = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
PORT_WIRING
{
}
}
MODULE payload_buffer
{
class = "altera_avalon_onchip_memory2";
class_version = "5.0";
iss_model_name = "altera_memory";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/payload_buffer.v";
Synthesis_Only_Files = "";
}
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "M4K";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "2048";
Size_Multiple = "1";
contents_info = "QUARTUS_PROJECT_DIR/payload_buffer.hex 1146296546 ";
MAKE
{
TARGET delete_placeholder_warning
{
payload_buffer
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET hex
{
payload_buffer
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2hex $(ELF) 0x00020000 0x207FF --width=16 $(QUARTUS_PROJECT_DIR)/payload_buffer.hex --create-lanes=0";
Dependency = "$(ELF)";
Target_File = "$(QUARTUS_PROJECT_DIR)/payload_buffer.hex";
}
}
TARGET sim
{
payload_buffer
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "10";
Is_Enabled = "1";
}
PORT byteenable
{
direction = "input";
type = "byteenable";
width = "2";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "16";
Is_Enabled = "1";
}
PORT write
{
direction = "input";
type = "write";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "16";
Is_Enabled = "1";
}
PORT clken
{
Is_Enabled = "1";
default_value = "1'b1";
direction = "input";
type = "clken";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "10";
Data_Width = "16";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "2048";
Read_Latency = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00020000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
Is_Channel = "1";
Is_Writable = "1";
}
}
SLAVE s2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Address_Width = "10";
Data_Width = "16";
Has_IRQ = "0";
Read_Wait_States = "0";
Write_Wait_States = "0";
Address_Span = "2048";
Read_Latency = "1";
Is_Enabled = "0";
Is_Channel = "1";
Is_Writable = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
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