radix = "binary";
               conditional = "1";
            }
            SIGNAL e
            {
               name = "readdata";
               radix = "hexadecimal";
            }
            SIGNAL f
            {
               name = "writedata";
               radix = "hexadecimal";
               conditional = "1";
            }
         }
      }
      PORT_WIRING 
      {
      }
   }
   MODULE jtag_uart_0
   {
      class = "altera_avalon_jtag_uart";
      class_version = "1.0";
      iss_model_name = "altera_avalon_jtag_uart";
      SLAVE avalon_jtag_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Address_Width = "1";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            JTAG_Hub_Base_Id = "0x04006E";
            JTAG_Hub_Instance_Id = "0";
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x00030000";
            Is_Base_Locked = "1";
            Connection_Limit = "1";
         }
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               direction = "output";
               width = "32";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               direction = "input";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               direction = "input";
               width = "32";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               direction = "output";
               width = "1";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Iss_Launch_Telnet = "0";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "<br>Write Depth: 64; Write IRQ Threshold: 8
                <br>Read  Depth: 64; Read  IRQ Threshold: 8";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "64";
         read_depth = "64";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         read_le = "1";
         write_le = "1";
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL av_irq
            {
               name = "av_irq";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE sysid
   {
      class = "altera_avalon_sysid";
      class_version = "4.0";
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT address
            {
               direction = "input";
               type = "address";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               direction = "output";
               type = "readdata";
               width = "32";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Has_IRQ = "0";
            Address_Width = "1";
            Data_Width = "32";
            Base_Address = "0x00040000";
            Address_Alignment = "native";
            Read_Wait_States = "1";
            Write_Wait_States = "0";
            Read_Latency = "0";
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "NC";
            }
            Is_Base_Locked = "1";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         View 
         {
            Settings_Summary = "System ID (at last Generate):<br> <b>0A0A16FC</b>    (unique ID tag) <br> <b>445318E5</b> (timestamp: Sat Apr 29, 2006 @3:42 PM)";
            Is_Collapsed = "1";
            MESSAGES 
            {
            }
         }
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         value0 = "1686625497u";
         value1 = "1079118575u";
         id = "168433404u";
         timestamp = "1146296549u";
         MAKE 
         {
            TARGET verifysysid
            {
               verifysysid 
               {
                  All_Depends_On = "0";
                  Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x00040000 --id=168433404 --timestamp=1146296549";
                  Is_Phony = "1";
                  Target_File = "dummy_verifysysid_file";
               }
            }
         }
      }
   }
   MODULE asmi
   {
      class = "altera_avalon_asmi";
      class_version = "2.1";
      SLAVE asmi_control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Nonvolatile_Storage = "1";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "16";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "1";
            }
            Base_Address = "0x00060000";
            Is_Base_Locked = "1";
         }
         PORT_WIRING 
         {
            PORT asmi_select
            {
               direction = "input";
               type = "chipselect";
               width = "1";
               Is_Enabled = "1";
            }
            PORT clk
            {
               direction = "input";
               type = "clk";
               width = "1";
               Is_Enabled = "1";
            }
            PORT data_from_cpu
            {
               direction = "input";
               type = "writedata";
               width = "16";
               Is_Enabled = "1";
            }
            PORT data_to_cpu
            {
               direction = "output";
               type = "readdata";
               width = "16";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               direction = "output";
               type = "dataavailable";
               width = "1";
               Is_Enabled = "1";
            }
            PORT endofpacket
            {
               direction = "output";
               type = "endofpacket";
               width = "1";
               Is_Enabled = "1";
            }
            PORT irq
            {
               direction = "output";
               type = "irq";
               width = "1";
               Is_Enabled = "1";
            }
            PORT mem_addr
            {
               direction = "input";
               type = "address";
               width = "3";
               Is_Enabled = "1";
            }
            PORT read_n
            {
               direction = "input";
               type = "read_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               direction = "output";
               type = "readyfordata";
               width = "1";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               direction = "input";
               type = "reset_n";
               width = "1";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               direction = "input";
               type = "write_n";