/* sysCache.c - secondary (L2) cache library for the Hawk SMC *//* Copyright 1984-2001 Wind River Systems, Inc. *//* Copyright 1996-2001 Motorola, Inc., All Rights Reserved. *//*modification history--------------------01b,20jun01,srr  Added support for Nitro.01a,31aug00,dmw  Written (from version 01c of mv5100/sysCache.c).*//*DESCRIPTIONThis library provides L2 cache support, and is derived fromcode supplied by Motorola.Support is included for initializing/enabling the L2 Cache on boot andenabling/disabling the L2 Cache with system calls.  Only Inline caches aresupported since there are no VPD-based boards with a look-aside cache.Parameters used to configured the L2 controller are gathered from the L2Cache Record in the VPD.*//* includes */#include "vxWorks.h"#include "sysCache.h"#define SYNC WRS_ASM("sync")#if defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_CACHE_L2)/* defines */#define BOARD_CONV_SHIFT  25/* forward declarations */STATUS           sysL2CacheInit (void);LOCAL STATUS     sysL2InlineCacheInit (void);void             sysL2CacheEnable (void);LOCAL void       sysL2InlineCacheEnable (void);void             sysL2CacheDisable (void);LOCAL void       sysL2InlineCacheDisable (void);void             sysL2CacheFlush (void);LOCAL void       sysL2InlineCacheFlush (void);void             sysL2CacheInvFunc (void);LOCAL void       sysL2InlineCacheInvFunc (void);LOCAL STATUS     sysL2CacheInfoGet(UCHAR, UCHAR *);LOCAL UINT       sysL2InlineCacheSize (void);LOCAL UINT       sysL2InlineCacheSpd (void);/* externals */IMPORT UINT sysL2crGet (void);IMPORT void sysL2crPut (UINT regVal);IMPORT UINT sysGetMpuSpd (void);IMPORT void sysMaxL2Disable(void);IMPORT void sysMaxL2InvFunc(void);IMPORT void sysMaxL2Flush(void);IMPORT VOIDFUNCPTR _pSysL2CacheInvFunc ;IMPORT VOIDFUNCPTR _pSysL2CacheEnable  ;IMPORT VOIDFUNCPTR _pSysL2CacheFlush   ;IMPORT VOIDFUNCPTR _pSysL2CacheDisable ;LOCAL UINT boardConvTable[] =    {    0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x0, 0x0, 0x0,    0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0    };LOCAL UINT boardFreqTable[] =    {    10, 10, 15, 20, 25, 30, 10, 10,    10, 10, 10, 10, 10, 10, 10, 10    };LOCAL VPD_PACKET * pVpdL2CachePacket = NULL;/******************************************************************************** sysL2CacheInfoGet - Get L2 Cache Info from the VPD.** This routine parses the VPD data structure for a L2 cache record and returns* field information in the record based on the L2CachePacketField that is* passed to it. ** RETURNS: OK, or ERROR if VPD L2 cache record missing or corrupt.** SEE ALSO: sysL2InlineCacheInit(), sysL2GetCacheSize()*/ LOCAL STATUS sysL2CacheInfoGet    (    UCHAR L2CachePacketFieldId,  /* Id for L2 cache record */    UCHAR * pL2CachePacketField  /* pointer to field information */    )    {    UINT i, fieldSize = 0;    BOOL fieldError = FALSE;    if (pVpdL2CachePacket == NULL)        {        /* Extract a VPD L2 Cache Packet */        if (sysVpdPktGet(VPD_PID_L2, 0, &sysVpdPkts[0], &pVpdL2CachePacket)            == ERROR)            return (ERROR);        }    /* Determine field length and if the field has a valid parameter */    switch (L2CachePacketFieldId)        {        case L2C_MID:        case L2C_DID:           fieldSize = 2;           break;        case L2C_DDW:        case L2C_NOD:        case L2C_NOC:        case L2C_CW:        case L2C_ASSOCIATE:            fieldSize = 1;            break;        case L2C_TYPE:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_TYPE_INLINE)                fieldError = TRUE;            else                fieldSize = 1;            break;        case L2C_OPERATIONMODE:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_OM_WB)                fieldError = TRUE;            else                fieldSize = 1;            break;        case L2C_ERROR_DETECT:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_ED_ECC)                fieldError = TRUE;            else                fieldSize = 1;            break;        case L2C_SIZE:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_SIZE_4M)                fieldError = TRUE;            else                fieldSize = 1;            break;        case L2C_TYPE_BACKSIDE:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_TYPE_BS_BNP)                fieldError = TRUE;            else                fieldSize = 1;            break;        case L2C_RATIO_BACKSIDE:            if (pVpdL2CachePacket->data[L2CachePacketFieldId] > L2C_RATIO_3_1)                fieldError = TRUE;            else                fieldSize = 1;                break;        default:            fieldError= TRUE;        break;        }    if (!fieldError)       {       if (fieldSize == 1)           pL2CachePacketField[0] =               pVpdL2CachePacket->data[L2CachePacketFieldId];        else           for (i=0; i<fieldSize; i++)               pL2CachePacketField[i] =                   pVpdL2CachePacket->data[L2CachePacketFieldId+i];       return OK;       }    else       return ERROR;    }/******************************************************************************** sysL2CacheInit - initialize the L2 cache ** This routine initializes and enables L2 cache(s) support. ** RETURNS: OK, or ERROR if cache is not present or not supported.** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/ STATUS sysL2CacheInit (void)    {    STATUS status = OK;    /* check for presence of L2 cache */    if (sysL2InlineCacheSize() != 0)        status |= sysL2InlineCacheInit();    return (status);    }/******************************************************************************** sysL2InlineCacheInit - initialize the L2 in-line cache.** This routine initializes and enables L2 in-line cache support.** RETURNS: OK, or ERROR if cache is not present or not supported.*/ LOCAL STATUS sysL2InlineCacheInit(void)    {    UINT l2CacheSize;    UINT l2crVal;    UCHAR l2CacheType, l2CacheRatio;    /* check for presence of L2 cache */    if ((l2CacheSize = sysL2InlineCacheSize()) == 0)        return(ERROR);        /* No L2 cache to init */    /* Initialize RAM type, output hold, differential clock */    if (sysL2CacheInfoGet(L2C_TYPE_BACKSIDE, &l2CacheType) == ERROR)        {        sysDebugMsg ("L2 cache record missing or corrupt.  L2 Cache Disabled.",                     CONTINUE_EXECUTION);        return(ERROR);        /* VPD Error */        }    switch ( l2CacheType )        {        case L2C_TYPE_BS_LWP:          /* Late Write, with Parity */        case L2C_TYPE_BS_LWNP:        /* Late Write, without Parity */        /*         * L2PE  = No parity enable         * L2RAM = Pipe reg-reg sync late-write         * L2OH  = 1.0ns         * L2DF  = Diff clock         */              l2crVal = MPC750_L2CR_RAM_PLTWR |              MPC750_L2CR_OH_1NS |              MPC750_L2CR_DF;        break;    case L2C_TYPE_BS_BP:          /* Burst with parity */    case L2C_TYPE_BS_BNP:         /* Burst, without Parity */        /*         * L2PE  = No parity enable         * L2RAM = Pipe reg-reg sync burst         * L2OH  = 0.5ns         * L2DF  = Nondiff clock         */        l2crVal = MPC750_L2CR_RAM_PBRST;              break;    default:        l2crVal = 0;        break;    }    /* Initialize the L2 clock ratio */        if (sysL2CacheInfoGet(L2C_RATIO_BACKSIDE, &l2CacheRatio) == ERROR)        {        sysDebugMsg("L2 cache record missing or corrupt.  L2 cache disabled.",                    CONTINUE_EXECUTION);        return (ERROR);        }    l2crVal |= boardConvTable[l2CacheRatio] << BOARD_CONV_SHIFT;    /*     * if L2 speed is below normal L2 speed threshold, set slow bit in L2     * cache control register.     */    if (sysL2InlineCacheSpd() < MPC750_L2_CACHE_SPEED_THRESHOLD)        l2crVal |= MPC750_L2CR_SL;    /* Set the Cache size */    switch (l2CacheSize)        {        case L2C_MEM_256K:            l2crVal |= MPC750_L2CR_256K;            break;        case L2C_MEM_512K:            l2crVal |= MPC750_L2CR_512K;            break;        case L2C_MEM_1M:            l2crVal |= MPC750_L2CR_1024K;            break;        case L2C_MEM_2M:            l2crVal |= MPC750_L2CR_2048K;            break;        }    /* Write out the L2 cache control register */    sysL2crPut(l2crVal);    /* Invalidate the L2 cache */    l2crVal |= MPC750_L2CR_I;    sysL2crPut(l2crVal);    SYNC;    /* wait for all memory transactions to finish */    while (sysL2crGet() & MPC750_L2CR_IP)        ;    l2crVal &= ~MPC750_L2CR_I;    sysL2crPut(l2crVal);