/* Enable the L2 cache */    sysL2InlineCacheEnable();    /* Enable access to cache functionality to OS */    _pSysL2CacheEnable  = &sysL2CacheEnable;    _pSysL2CacheFlush   = &sysL2CacheFlush;    _pSysL2CacheDisable = &sysL2CacheDisable;    _pSysL2CacheInvFunc = &sysL2CacheInvFunc;     return (OK);    }/******************************************************************************** sysL2CacheFlush - flush the L2 cache(s)* * This routine flushes the L2 cache(s) if either or both were* previously initialized using sysL2CacheInit().** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/ void sysL2CacheFlush (void)    {    UINT cacheSize;    if ((cacheSize = sysL2InlineCacheSize()) != 0)        sysL2InlineCacheFlush();    }/******************************************************************************** sysL2InlineCacheFlush - flush the L2 cache(s)* * Flush by reading one word from each cache line within a cache* enabled buffer.  Note that this buffer should be twice the size of* the L2 cache to override the pseudo-LRU replacement algorithm.** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/LOCAL void sysL2InlineCacheFlush (void)    {    int lockKey;    register int i;    register ULONG tmp;    lockKey=intLock();    if (CPU_TYPE == CPU_TYPE_750)        {        if (vxHid0Get() & _PPC_HID0_DCE)            {            /* flush the inline L2 cache */            for (i = 2*sysL2InlineCacheSize() - 32; i >= 0; i -= 32 )            tmp = *(ULONG *)(RAM_LOW_ADRS + i);            }       }    else        {       sysMaxL2Flush();       }    intUnlock(lockKey);    }/******************************************************************************** sysL2CacheInvFunc - Invalidate the L2 cache(s)* * This routine invalidates the L2 cache(s) if either or both were* previously initialized using sysL2CacheInit().  Calling this * routine invalidates the L2 tag bits.** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/ void sysL2CacheInvFunc (void)    {    UINT cacheSize;    if ((cacheSize = sysL2InlineCacheSize()) != 0)        sysL2InlineCacheInvFunc();    }/******************************************************************************** sysL2InlineCacheInvFunc - Invalidate the L2 cache(s)* * Disables interrupts and calls the function to invalidate the L2 cache.** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/LOCAL void sysL2InlineCacheInvFunc (void)    {    int lockKey;    lockKey=intLock();    sysMaxL2InvFunc();    intUnlock(lockKey);    }/******************************************************************************** sysL2InlineCacheEnable - enable the L2 in-line cache* * RETURNS: N/A*/ LOCAL void sysL2InlineCacheEnable (void)    {    UINT l2crVal;     if (sysL2InlineCacheSize() == 0)        return;                   /* Return if no L2 Inline cache present */    /* make sure L2 is already disabled */    if ( ((l2crVal = sysL2crGet()) & MPC750_L2CR_E) == 0)        {        l2crVal |= MPC750_L2CR_E;        sysL2crPut(l2crVal);        }    }/******************************************************************************** sysL2CacheDisable - disable the L2 cache(s)* * This routine disables the L2 cache(s) if either or both were* previously initialized using sysL2CacheInit().  Calling this * routine invalidates the L2 tag bits.** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/ void sysL2CacheDisable (void)    {    UINT cacheSize;    if ((cacheSize = sysL2InlineCacheSize()) != 0)        sysL2InlineCacheDisable();    }/******************************************************************************** sysL2InlineCacheDisable - disable the L2 in-line cache** If the in-line cache is enabled, this routine disables it via the following* steps:** .IP "1."* Flush by reading one word from each cache line within a cache* enabled buffer.  Note that this buffer should be twice the size of* the L2 cache to override the pseudo-LRU replacement algorithm.* .IP "2."* Turn off the cache enable bit in the L2CR.* .IP "3."* Invalidate the L2 cache contents.** RETURNS: N/A*/ LOCAL void sysL2InlineCacheDisable (void)    {    register ULONG tmp;    register ULONG l2crVal;    register int i;    int  lockKey;          /* interrupt lock key */    lockKey = intLock();   /* disable interrupts */    if ((l2crVal = sysL2crGet()) & MPC750_L2CR_E)        {        if (CPU_TYPE == CPU_TYPE_750)            {            if (vxHid0Get() & _PPC_HID0_DCE)                {                /* flush the inline L2 cache */                for (i = 2*sysL2InlineCacheSize() - 32; i >= 0; i -= 32 )                tmp = *(ULONG *)(RAM_LOW_ADRS + i);                }            /* disable the inline L2 cache */            SYNC;            l2crVal &= ~MPC750_L2CR_E;            sysL2crPut(l2crVal);            SYNC;            /* invalidate the inline L2 cache */            sysL2crPut(l2crVal | MPC750_L2CR_I);            SYNC;    /* wait for all memory transactions to finish */            while (sysL2crGet() & MPC750_L2CR_IP)                 ;            sysL2crPut(l2crVal);            }        else                                            {            sysMaxL2Disable();            l2crVal &= ~MPC750_L2CR_E;            /* invalidate the inline L2 cache */            sysL2crPut(l2crVal | MPC750_L2CR_I);            SYNC;    /* wait for all memory transactions to finish */            }        }        intUnlock(lockKey);             /* re-enable interrupts */    }/******************************************************************************** sysL2InlineCacheSize() - Determine size of the L2 in-line cache.** This function returns the size of the L2 in-line cache.  If no L2* in-line cache is present, the size returned is zero so this function's* return value can be used like a boolean to determine if the L2 in-line* cache is actually present.** RETURNS: Size of L2 in-line cache or zero if in-line cache not present.** NOTE: Don't confuse the L2 in-line cache with the other possible type* of cache, referred to as the "glance" or "lookaside" cache.*/ LOCAL UINT sysL2InlineCacheSize()    {    STATUS size;    UCHAR l2CacheSize;    if (CPU_TYPE != CPU_TYPE_750 && CPU_TYPE != CPU_TYPE_MAX &&        CPU_TYPE != CPU_TYPE_NITRO)        return(0);    /* Not an Arthur/Max/Nitro chip so no in-line L2 cache */    if (sysL2CacheInfoGet(L2C_SIZE, &l2CacheSize) == ERROR)        {        sysDebugMsg ("L2 cache record missing or corrupt.  L2 cache disabled.",                     CONTINUE_EXECUTION);        return (0);        }    switch ( l2CacheSize )        {        case L2C_SIZE_256K:            size = L2C_MEM_256K;            break;        case L2C_SIZE_512K:            size = L2C_MEM_512K;            break;        case L2C_SIZE_1M:            size = L2C_MEM_1M;            break;        case L2C_SIZE_2M:            size = L2C_MEM_2M;            break;        case L2C_SIZE_4M:            size = L2C_MEM_4M;            break;        default:            size = L2C_MEM_NONE;            break;        }    return(size);    }/******************************************************************************** sysL2InlineCacheSpd() - Determine speed of the L2 in-line cache.** This function returns the speed of the L2 in-line cache.  If no L2* in-line cache is present, the speed returned is zero so this function's* return value can be used like a boolean to determine if the L2 in-line* cache is actually present.** RETURNS: Speed of L2 in-line cache or zero if in-line cache not present.** NOTE: Don't confuse the L2 in-line cache with the other possible type* of cache, referred to as the "glance" or "lookaside" cache.*/ LOCAL UINT sysL2InlineCacheSpd(void)    {    UINT l2Spd;    UCHAR l2CacheRatio;    if (sysL2InlineCacheSize() == 0)        return(0);       if (sysL2CacheInfoGet(L2C_RATIO_BACKSIDE, &l2CacheRatio) == ERROR)        {        sysDebugMsg ("L2 cache record missing or corrupt.  L2 Cache Disabled.",                     CONTINUE_EXECUTION);        return(ERROR);          /* VPD Error */        }    l2Spd = (sysGetMpuSpd() / boardFreqTable[l2CacheRatio]) * 10;    return(l2Spd);    }   /******************************************************************************** sysL2CacheEnable - enable the L2 cache(s)* * This routine enables the L2 cache(s).* It checks for the presence of either L2 cache * and ensures that the cache(s) is(are) disabled.** RETURNS: N/A** SEE ALSO: sysL2CacheInit(), sysL2CacheEnable(), sysL2CacheDisable()*/ void sysL2CacheEnable (void)    {    UINT cacheSize;    if ((cacheSize = sysL2InlineCacheSize()) != 0)        sysL2InlineCacheEnable();    }#endif    /* INCLUDE_CACHE_SUPPORT && INCLUDE_CACHE_L2 */