*(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_0_REG   = SHORTSWAP(0);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_1 = 0;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_1    = 0;     *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_1_REG      = inboundSizeCode(0);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_1_REG   = SHORTSWAP(0);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_2 = 0;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_2    = 0;     *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_2_REG      = inboundSizeCode(0);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_2_REG   = SHORTSWAP(0);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_3 = 0;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_3    = 0;     *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_3_REG      = inboundSizeCode(0);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_3_REG   = SHORTSWAP(0);    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT0_ADDR_RANGE_REG = 0xF000F1FF;    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT0_ATTR_REG |= 0xE1F00000;    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT1_ADDR_RANGE_REG = 0xFF80FFEF;    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT1_ATTR_REG |= 0xEBF00000;    EIEIO_SYNC;#ifdef INCLUDE_PRPMC800XT    *(UINT32 *)HARRIER_XPORT2_ADDR_RANGE_REG = 0xFF10FF1F;    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT2_ATTR_REG |= 0xE0F00000;    EIEIO_SYNC;    *(UINT32 *)HARRIER_XPORT3_ADDR_RANGE_REG = 0xFF20FF2F;     EIEIO_SYNC;     *(UINT32 *)HARRIER_XPORT3_ATTR_REG |= 0xE0F00000;     EIEIO_SYNC;#endif /* INCLUDE_PRPMC800XT */    /* Clear error exceptions */    *(UINT32 *)HARRIER_ERROR_EXCEPTION_CLEAR_REG = 0;    EIEIO_SYNC;    /* Enable the PCI Bridge */    *(UINT16 *)HARRIER_PHB_COMMAND_REG |= HARRIER_CMMD_MTSR | 					  HARRIER_CMMD_MEMSP;    }/********************************************************************************* sysHarrierPhbInit2 - initialize the Harrier PHB registers which require VPD** This function performs the second phase of the Harrier PPC-bus registers.* These registers require information contained in the VPD.** RETURNS: N/A*/void sysHarrierPhbInit2 (void)    {    *(UINT32 *)HARRIER_PPC_CLOCK_FREQUENCY_REG =         256 - ((sysGetBusSpd () + (MHZ/2))/MHZ);    EIEIO_SYNC;    }/******************************************************************************** sysHarrierInitPhbExt - initialize the extended portion of the Harrier PHB * PCI header.** This routine initializes the extended portion of the PCI header for the* Motorola Harrier PCI-Host Bridge Controller (PHB).** RETURNS: OK*/STATUS sysHarrierInitPhbExt (void)    {    /*     * Partially initialize the Harrier's Slave decoders (attribute and     * size).  pciAutoConfig(), which has not yet run, will be setting     * the BAR base addresses after which we will set the translations     * in sysHarrierInitInpOffset().     *     * These decoders map addresses on the PCI bus to the CPU for     * access to local DRAM.     *     * Because hardware can read past real memory, it is necessary to disable     * Read Ahead for the last 64k of physical memory (DRAM).     */    /* Setup Inbound Translation Window some low DRAM onto PCI bus. */    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_0   = PCI2CPU_0_ATTR;    *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_0_REG     =               inboundSizeCode(PCI2CPU_0_SIZE);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_0_REG  =                SHORTSWAP(PCI2CPU_0_TARG);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_1   = PCI2CPU_1_ATTR;    *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_1_REG     =               inboundSizeCode(PCI2CPU_1_SIZE);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_1_REG  =                SHORTSWAP(PCI2CPU_1_TARG);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_2   = PCI2CPU_2_ATTR;    *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_2_REG     =               inboundSizeCode(PCI2CPU_2_SIZE);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_2_REG  =                SHORTSWAP(PCI2CPU_2_TARG);    EIEIO_SYNC;    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_3   = PCI2CPU_3_ATTR;    *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_3_REG     = 	      inboundSizeCode(PCI2CPU_3_SIZE);    *(UINT16 *)HARRIER_INBOUND_TRANSLATION_OFFSET_3_REG  =                SHORTSWAP(PCI2CPU_3_TARG);    EIEIO_SYNC;    /* Clear PCI configuration cycles hold off bit. */    *(UINT32 *)HARRIER_BRIDGE_PCI_CONTROLSTATUS_REG &=                ~HARRIER_BPCS_XCSR_CSH;    /*      * Set the PCI Bus Enumeration Ready bit and wait for the PCI Bus     * Enumeration status bit to flip before proceeding.     */    *(UINT32 *)HARRIER_MISC_CONTROL_STATUS_REG |= HARRIER_MCSR_EREADY;    EIEIO_SYNC;    while ((*(volatile UINT32 *)(HARRIER_MISC_CONTROL_STATUS_REG)) & 			        (HARRIER_MCSR_EREADYS == 0))	;    return(OK);    }/******************************************************************************** sysHarrierInitPhbExt2 - Fix address tranlation offsets.** This routine calculates the address translation offsets following PCI* Auto Configuration.** RETURNS: OK*/STATUS sysHarrierInitPhbExt2 (void)    {    UINT32 barVal;    UINT32 whichBar = HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0;    UINT32 whichOffset = HARRIER_INBOUND_TRANSLATION_OFFSET_0_REG;    UINT32 barOffset;    int    barCount = 0;    for ( ; barCount < 4; barCount++)        {        barVal =             LONGSWAP(*(UINT32 *)(whichBar + (barCount * 4))) & 		     HARRIER_PCFS_ITBAR_BASE_MASK;        barOffset = (0x0 - barVal) >> 16;        *(UINT16 *)(whichOffset + (barCount * 8))  =             SHORTSWAP(barOffset);        }    return(OK);    }/******************************************************************************** sysHarrierFixInp - fix input offsets if Harrier revision 1.* * This routine conditionally changes the input offset registers if we're* working with a Harrier revision 1.** RETURNS: OK*/STATUS sysHarrierFixInp (void)    {    USHORT revisionId;      revisionId = ((*(UINT32 *)HARRIER_REGISTER_REVISION_ID) >>                              HARRIER_REVISION_ID_SHIFT_MASK);   /*     * Harrier Errata 7 - Inbound map decoders    * The specification states that the PCI address bits which     * correspond with the programmable bits position within the BAR    * are set to zero before the offset is added to the PCI address    * to create the PowerPC bus address. The address bits are not     * set to zero before the offset is added. This means the offset    * is dependent on the base address.    * e.g. If the PCI base address is 0x08000000 and the size is 128M    * and the offset is 0, the incoming PCI address should map to    * PowerPC address 0.    */   if (revisionId == HARRIER_REVISION_1)       {       /*        * Re-evaluate the Inbound Translation Offset from base addr.        * This fix is required only for the Harrier I chipset        */       (void)sysHarrierInitPhbExt2 ();        }    return (OK);    }/******************************************************************************** sysHarrierErrClr - Clear error conditions in Harrier** This routine clears any existing errors in the Motorola Harrier PCI Host * Bridge Controller.** RETURNS: N/A*/void sysHarrierErrClr (void)    {    *(UINT32 *)HARRIER_ERROR_EXCEPTION_CLEAR_REG = 0;    }