?? scan.rpt
字號:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\scan.rpt
scan
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 14 LCELL s 1 0 1 0 GW~1
- 8 - B 14 LCELL s 1 0 1 0 SW~1
- 7 - B 14 OR2 3 0 1 0 |74157:1|Y1 (|74157:1|:22)
- 3 - B 14 OR2 3 0 1 0 |74157:1|Y2 (|74157:1|:23)
- 1 - B 14 OR2 3 0 1 0 |74157:1|Y3 (|74157:1|:24)
- 6 - B 14 OR2 3 0 1 0 |74157:1|Y4 (|74157:1|:25)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
scan
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 4/ 48( 8%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan\maxplus\cunchuqi\scan.rpt
scan
** EQUATIONS **
G0 : INPUT;
G1 : INPUT;
G2 : INPUT;
G3 : INPUT;
SCAN_CLK : INPUT;
S0 : INPUT;
S1 : INPUT;
S2 : INPUT;
S3 : INPUT;
-- Node name is 'GW'
-- Equation name is 'GW', type is output
GW = !_LC2_B14;
-- Node name is 'GW~1'
-- Equation name is 'GW~1', location is LC2_B14, type is buried.
-- synthesized logic cell
_LC2_B14 = LCELL( SCAN_CLK);
-- Node name is 'OUT0'
-- Equation name is 'OUT0', type is output
OUT0 = _LC7_B14;
-- Node name is 'OUT1'
-- Equation name is 'OUT1', type is output
OUT1 = _LC3_B14;
-- Node name is 'OUT2'
-- Equation name is 'OUT2', type is output
OUT2 = _LC1_B14;
-- Node name is 'OUT3'
-- Equation name is 'OUT3', type is output
OUT3 = _LC6_B14;
-- Node name is 'SW'
-- Equation name is 'SW', type is output
SW = _LC8_B14;
-- Node name is 'SW~1'
-- Equation name is 'SW~1', location is LC8_B14, type is buried.
-- synthesized logic cell
_LC8_B14 = LCELL( SCAN_CLK);
-- Node name is '|74157:1|:22' = '|74157:1|Y1'
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ001);
_EQ001 = G0 & !SCAN_CLK
# SCAN_CLK & S0;
-- Node name is '|74157:1|:23' = '|74157:1|Y2'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ002);
_EQ002 = G1 & !SCAN_CLK
# SCAN_CLK & S1;
-- Node name is '|74157:1|:24' = '|74157:1|Y3'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ003);
_EQ003 = G2 & !SCAN_CLK
# SCAN_CLK & S2;
-- Node name is '|74157:1|:25' = '|74157:1|Y4'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ004);
_EQ004 = G3 & !SCAN_CLK
# SCAN_CLK & S3;
Project Information e:\shiyan\maxplus\cunchuqi\scan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,448K
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