?? mainstoneii.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this sample source code is subject to the terms of the Microsoft
// license agreement under which you licensed this sample source code. If
// you did not accept the terms of the license agreement, you are not
// authorized to use this sample source code. For the terms of the license,
// please see the license agreement between you and Microsoft or, if applicable,
// see the LICENSE.RTF on your install media or the root of your tools installation.
// THE SAMPLE SOURCE CODE IS PROVIDED "AS IS", WITH NO WARRANTIES.
//
//------------------------------------------------------------------------------
//
// File: mainstoneii.h
//
// This header file contains Mainstone II specific definitions.
//
#ifndef __MAINSTONEII_H__
#define __MAINSTONEII_H__
//
// MainstoneII: (on PDC): nCS0: Boot FLASH (32MB - 64MB on the MCPII module)
//
#define MAINSTONEII_BASE_PA_BOOT_FLASH 0x00000000
#ifdef MCPII_MODULE
#define MAINSTONEII_SIZE_BOOT_FLASH 0x04000000
#else
#define MAINSTONEII_SIZE_BOOT_FLASH 0x02000000
#endif
//
// MainstoneII: nCS1: Secondary FLASH (32MB)
//
#define MAINSTONEII_BASE_PA_SECONDARY_FLASH 0x04000000
//
// MainstoneII: nCS2: Board-Level Registers (FPGA)
//
#define MAINSTONEII_BASE_REG_PA_FPGA 0x08000000
//
// MainstoneII: nCS2 (on PDC): SRAM (2 MB)
//
#define MAINSTONEII_BASE_PA_SRAM 0x0A000000
//
// MainstoneII: nCS3: not used, not mapped. Used as PCMCIA PSKTSEK signal on MainstoneII.
//
#define MAINSTONEII_BASE_PA_CS3 0x0C000000
//
// MainstoneII: nCS4: Ethernet (SMSC 91C111)
//
#define MAINSTONEII_BASE_REG_PA_SMSC_ETHERNET 0x10000000
//
// MainstoneII: nCS5: eXpansion Board Header
//
#define MAINSTONEII_BASE_PA_XDC 0x14000000
//
// MainstoneII: nCS5: eXpansion Board Header
//
#define MAINSTONEII_BASE_PA_SDRAM 0xA0000000
#ifdef SDRAM_SIZE_64_MB
#define MAINSTONEII_SIZE_SDRAM 0x04000000
#else
#define MAINSTONEII_SIZE_SDRAM 0x08000000
#endif
//
// MainstoneII: Board Level Registers
//
typedef struct
{
UINT32 rsvd0[4]; // 0800_0000 -> 0800_000F
UINT32 hex_led; // 0800_0010 -> 0800_0013
UINT32 hex_led2; // 0800_0014 -> 0800_0017
UINT32 rsvd1[10]; // 0800_0018 -> 0800_003F
UINT32 disc_blnk_led; // 0800_0040 -> 0800_0043
UINT32 rsvd2[7]; // 0800_0044 -> 0800_005F
UINT32 gpsw; // 0800_0060 -> 0800_0063
UINT32 rsvd3[7]; // 0800_0064 -> 0080_007F
UINT32 misc_wr; // 0800_0080 -> 0080_0083
UINT32 misc_wr2; // 0800_0084 -> 0080_0087
UINT32 misc_wr3; // 0800_0084 -> 0080_0087
UINT32 rsvd4[1]; // 0800_0088 -> 0800_008F
UINT32 misc_rd; // 0800_0090 -> 0800_0093
UINT32 rsvd5[11]; // 0800_0094 -> 0800_00BF
UINT32 int_msk_en; // 0800_00C0 -> 0800_00C3
UINT32 rsvd6[3]; // 0800_00C4 -> 0800_00CF
UINT32 int_set_clr; // 0800_00D0 -> 0800_00D3
UINT32 rsvd7[3]; // 0800_00D4 -> 0800_00DF
UINT32 pcmcia0_srcr; // 0800_00E0 -> 0800_00E3
UINT32 pcmcia1_srcr; // 0800_00E4 -> 0800_00E7
UINT32 rsvd8[2]; // 0800_00E8 -> 0800_00EF
UINT32 revid; // 0800_00F0 -> 0800_00F3
UINT32 scratch[3]; // 0800_00F4 -> 0800_00FF
} MAINSTONEII_BLR_REGS, *PMAINSTONEII_BLR_REGS;
// <BELOW ITEMS UNTOUCHED FROM COTULLA>
//
// GEDR Power GPIO bits - write to clear
//
#define GEDR_GPIO0_EDGE_CLR(reg) (reg = XLLP_GPIO_BIT_0)
#define GEDR_GPIO1_EDGE_CLR(reg) (reg = XLLP_GPIO_BIT_1)
//
// Power GPIO edge trigger macros
//
#define POWER_OFF_RISING_EDGE(reg) (reg |= XLLP_GPIO_BIT_1)
#define POWER_OFF_FALLING_EDGE(reg) (reg |= XLLP_GPIO_BIT_1)
//
// USB Cable edge trigger macros
//
#define USBCABLE_RISING_EDGE(reg) (reg |= XLLP_GPIO_BIT_0)
#define USBCABLE_FALLING_EDGE(reg) (reg |= XLLP_GPIO_BIT_0)
#define USBCABLE_RISING_EDGE_CLR(reg) (reg &= ~XLLP_GPIO_BIT_0)
#define USBCABLE_FALLING_EDGE_CLR(reg) (reg &= ~XLLP_GPIO_BIT_0)
//
// Processor Stepping Values
//
#define BULVERDE_CP15_A0_VAL 0x69054110
#define BULVERDE_CP15_A1_VAL 0x69054111
#define BULVERDE_CP15_B0_VAL 0x69054112
#define BULVERDE_JTAG_A0_VAL 0x09265013
#define BULVERDE_JTAG_A1_VAL 0x19265013
#define BULVERDE_JTAG_B0_VAL 0x29265013
//
// Mainstone: Board-Level Register Masks & Constants
//
//
// DISC/BLANK LED (On=0, Off=1: read/write)
// {*Use 1's complement to turn ON}
//
#define DISC_LED0_MASK (1 << 0)
#define DISC_LED1_MASK (1 << 1)
#define DISC_LED2_MASK (1 << 2)
#define DISC_LED3_MASK (1 << 3)
#define DISC_LED4_MASK (1 << 4)
#define DISC_LED5_MASK (1 << 5)
#define DISC_LED6_MASK (1 << 6)
#define DISC_LED7_MASK (1 << 7)
//
// GP SWITCHES (read-only) 1=noDOT, 0=DOT
//
#define SW12_MASK (0x1 << 15)
#define SW11_MASK (0x1 << 14)
#define SW7_MASK (0x1 << 13)
#define SW6_MASK (0x1 << 12)
#define SW10_MASK (0x1 << 11)
#define SW8_MASK (0x1 << 10)
#define SW4_MASK (0x1 << 9)
#define SW3_MASK (0x1 << 8)
#define HEXSW1_MASK (0xF << 4)
#define HEXSW0_MASK (0xF)
//
// GP Switches (GPSWR)
//
#define SW21_MASK (0x1 << 15)
#define SW20_MASK (0x1 << 14)
#define SW19_MASK (0x1 << 13)
#define SW18_MASK (0x1 << 12)
#define SW17_MASK (0x1 << 11)
#define SW16_MASK (0x1 << 10)
#define SW15_MASK (0x1 << 9)
#define SW14_MASK (0x1 << 8)
#define HEXSW13_MASK (0xF << 4)
#define HEXSW12_MASK (0xF)
//
// MISC_WR 1 (read/write)
//
// Masks
//
#define LCD_CTL_MASK (0x1 << 13)
#define MS_ON_MASK (0x1 << 12)
#define MMC_ON_MASK (0x1 << 11)
#define MS_SEL_MASK (0x1 << 10)
#define BB_SEL_MASK (0x1 << 9)
#define nBT_OFF_MASK (0x1 << 8)
#define BTDTR_MASK (0x1 << 7)
#define IRDA_MD_MASK (0x3 << 5)
#define IRDA_FIR_MASK (0x1 << 4)
#define GREEN_LED_MASK (0x1 << 3)
#define PDC_CTL_MASK (0x1 << 2)
#define MTR_ON_MASK (0x1 << 1)
#define SYSRESET_MASK (0x1)
// Constants
//
#define IRDA_MD_ONETHIRD (0x3 << 5)
#define IRDA_MD_TWOTHIRD (0x2 << 5)
#define IRDA_MD_SHUTDOWN (0x1 << 5)
//
// MISC_WR 2 (read/write)
//
#define NUSBC_SC_MASK (0x1 << 4)
#define I2S_SPKROFF_MASK (0x1 << 3)
#define AC97_SPKROFF_MASK (0x1 << 2)
#define RADIO_PWR_MASK (0x1 << 1)
#define RADIO_WAKE_MASK (0x1)
//
// MISC_RD (read-only)
//
#define nPENIRQ_MASK (0x1 << 9)
#define nMEMSTK_CD_MASK (0x1 << 8)
#define nMMC_CD_MASK (0x1 << 7)
#define nUSIM_CD_MASK (0x1 << 6)
#define USB_CBL_MASK (0x1 << 5)
#define TS_BUSY_MASK (0x1 << 4)
#define BTDSR_MASK (0x1 << 3)
#define BTRI_MASK (0x1 << 2)
#define BTDCD_MASK (0x1 << 1)
#define MMC_WP_MASK (0x1)
//
// INTERRUPT MASK/ENABLE (read/write: 0=Mask, 1=Enable)
// AND
// INTERRUPT SET/CLEAR (read/write: 0=Clear, 1=Set)
//
#define PCMCIA_S1_IRQ_MASK (0x1 << 15)
#define PCMCIA_S1_STSCHG_MASK (0x1 << 14)
#define PCMCIA_S1_CD_MASK (0x1 << 13)
#define PCMCIA_S0_IRQ_MASK (0x1 << 11)
#define PCMCIA_S0_STSCHG_MASK (0x1 << 10)
#define PCMCIA_S0_CD_MASK (0x1 << 9)
#define EXPBD_IRQ_MASK (0x1 << 7)
#define MSINS_MASK (0x1 << 6)
#define PENIRQ_MASK (0x1 << 5)
#define UCB1400_IRQ_MASK (0x1 << 4)
#define ETHERNET_IRQ_MASK (0x1 << 3)
#define USBCD_MASK (0x1 << 2)
#define USIMCD_MASK (0x1 << 1)
#define MMCCD_MASK (0x1)
//
// PCMCIA Socket 0 Status/Control
//
// Masks
//
#define PCMCIA_S0_nIRQ_MASK (0x1 << 10)
#define PCMCIA_S0_nSPKR_BVD2_MASK (0x1 << 9)
#define PCMCIA_S0_nSTSCHG_BVD1_MASK (0x1 << 8)
#define PCMCIA_S0_nVS_MASK (0x3 << 6)
#define PCMCIA_S0_nCD_MASK (0x1 << 5)
#define PCMCIA_S0_RESET_MASK (0x1 << 4)
#define PCMCIA_S0_PWR_MASK (0xF)
// Constants
//
#define PCMCIA_S0_PWR_A1VCC (0x1 << 3)
#define PCMCIA_S0_PWR_A0VCC (0x1 << 2)
#define PCMCIA_S0_PWR_A1VPP (0x1 << 1)
#define PCMCIA_S0_PWR_A0VPP (0x1)
//
// PCMCIA Socket 1 Status/Control
//
// Masks
//
#define PCMCIA_S1_nIRQ_MASK (0x1 << 10)
#define PCMCIA_S1_nSPKR_BVD2_MASK (0x1 << 9)
#define PCMCIA_S1_nSTSCHG_BVD1_MASK (0x1 << 8)
#define PCMCIA_S1_nVS_MASK (0x3 << 6)
#define PCMCIA_S1_nCD_MASK (0x1 << 5)
#define PCMCIA_S1_RESET_MASK (0x1 << 4)
#define PCMCIA_S1_PWR_MASK (0xF)
// Constants
//
#define PCMCIA_S1_PWR_A1VCC (0x1 << 3)
#define PCMCIA_S1_PWR_A0VCC (0x1 << 2)
#define PCMCIA_S1_PWR_A1VPP (0x1 << 1)
#define PCMCIA_S1_PWR_A0VPP (0x1)
#endif // __MAINSTONEII_H__.
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