`timescale 1ns/10ps
module hf_division13(data_in,clock,reset,data_out);

input [19:1] data_in;
input clock,reset;
output [18:1] data_out;

reg [18:1] data_out;

always@(posedge clock or negedge reset)
   begin
     if(!reset)
        data_out=0;
     else
       if(data_in[1]==1)
          data_out=(data_in+1)>>1;
       else
          data_out=data_in>>1;
   end
endmodule