// 該模塊為數字鎖相環

module dpll(
		clk	,	//clock
		rzcd	,	//code input double edge detection
		bsyn	);	//locked clock 
input  clk	;
input  rzcd	;
output bsyn	;

reg bps		;
reg bsyn	;
reg [1:0]pre	;	//edge detection 
reg [4:0]preset	;	//count setting 
reg [4:0]count	;	//count 

///////////////////////////////////////////////////////
//edge detection
always @(posedge clk)
begin
	pre[1]=pre[0];
	pre[0]=rzcd;
	if(pre==2'b01 || pre==2'b10)
		bps=1;
	else
		bps=0;	
end
///////////////////////////////////////////////////////
//form bit syn-pluse
always @(posedge clk) begin
	if(count==0)
		count=preset;
	else
		count=count-1;
	if(count<14 & count>=6)
		bsyn=1;
	else
		bsyn=0;
end
///////////////////////////////////////////////////////
//modify preset value
always @(posedge clk) begin
	if(bps==1)
		if(count<'b00110)
			preset='b10001;
		else if(count>'b00110)
			preset='b01111;
		else if(count=='b00110)
			preset='b10000;
end
///////////////////////////////////////////////////////
endmodule