?? 2413addr.h
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//=============================================================================
// File Name : 2413addr.h
// Function : S3C2413 Define Address Register
// History
// 0.0 : Programming start (September 15,2005)
//=============================================================================
#ifndef __2413ADDR_H__
#define __2413ADDR_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "option.h"
//chapter2 EBI
#define rEBIPR (*(volatile unsigned *)0x48800000) //Bus priority decision
#define rBANK_CFG (*(volatile unsigned *)0x48800004) //Bank Configuration
//chapter3 MOBILE DRAM CONTROLLER
#define rBANKCFG (*(volatile unsigned *)0x48000000) //Mobile DRAM configuration
#define rBANKCON1 (*(volatile unsigned *)0x48000004) //Mobile DRAM control
#define rBANKCON2 (*(volatile unsigned *)0x48000008) //Mobile DRAM timing control
#define rBANKCON3 (*(volatile unsigned *)0x4800000C) //Mobile DRAM (E)MRS
#define rREFRESH (*(volatile unsigned *)0x48000010) //Mobile DRAM refresh control
#define rTIMEOUT (*(volatile unsigned *)0x48000014) //Write Buffer Time out control
//chapter4 SSMC
#define rSMBIDCYR0 (*(volatile unsigned *)0x4F000000) //Bank0 idle cycle control
#define rSMBIDCYR1 (*(volatile unsigned *)0x4F000020) //Bank1 idle cycle control
#define rSMBIDCYR2 (*(volatile unsigned *)0x4F000040) //Bank2 idle cycle control
#define rSMBIDCYR3 (*(volatile unsigned *)0x4F000060) //Bank3 idle cycle control
#define rSMBIDCYR4 (*(volatile unsigned *)0x4F000080) //Bank0 idle cycle control
#define rSMBIDCYR5 (*(volatile unsigned *)0x4F0000A0) //Bank5 idle cycle control
#define rSMBWSTRDR0 (*(volatile unsigned *)0x4F000004) //Bank0 read wait state control
#define rSMBWSTRDR1 (*(volatile unsigned *)0x4F000024) //Bank1 read wait state control
#define rSMBWSTRDR2 (*(volatile unsigned *)0x4F000044) //Bank2 read wait state control
#define rSMBWSTRDR3 (*(volatile unsigned *)0x4F000064) //Bank3 read wait state control
#define rSMBWSTRDR4 (*(volatile unsigned *)0x4F000084) //Bank4 read wait state control
#define rSMBWSTRDR5 (*(volatile unsigned *)0x4F0000A4) //Bank5 read wait state control
#define rSMBWSTWRR0 (*(volatile unsigned *)0x4F000008) //Bank0 write wait state control
#define rSMBWSTWRR1 (*(volatile unsigned *)0x4F000028) //Bank1 write wait state control
#define rSMBWSTWRR2 (*(volatile unsigned *)0x4F000048) //Bank2 write wait state control
#define rSMBWSTWRR3 (*(volatile unsigned *)0x4F000068) //Bank3 write wait state control
#define rSMBWSTWRR4 (*(volatile unsigned *)0x4F000088) //Bank4 write wait state control
#define rSMBWSTWRR5 (*(volatile unsigned *)0x4F0000A8) //Bank5 write wait state control
#define rSMBWSTOENR0 (*(volatile unsigned *)0x4F00000C) //Bank0 output enable assertion delay control
#define rSMBWSTOENR1 (*(volatile unsigned *)0x4F00002C) //Bank1 output enable assertion delay control
#define rSMBWSTOENR2 (*(volatile unsigned *)0x4F00004C) //Bank2 output enable assertion delay control
#define rSMBWSTOENR3 (*(volatile unsigned *)0x4F00006C) //Bank3 output enable assertion delay control
#define rSMBWSTOENR4 (*(volatile unsigned *)0x4F00008C) //Bank4 output enable assertion delay control
#define rSMBWSTOENR5 (*(volatile unsigned *)0x4F0000AC) //Bank5 output enable assertion delay control
#define rSMBWSTWENR0 (*(volatile unsigned *)0x4F000010) //Bank0 write enable assertion delay control
#define rSMBWSTWENR1 (*(volatile unsigned *)0x4F000030) //Bank1 write enable assertion delay control
#define rSMBWSTWENR2 (*(volatile unsigned *)0x4F000050) //Bank2 write enable assertion delay control
#define rSMBWSTWENR3 (*(volatile unsigned *)0x4F000070) //Bank3 write enable assertion delay control
#define rSMBWSTWENR4 (*(volatile unsigned *)0x4F000090) //Bank4 write enable assertion delay control
#define rSMBWSTWENR5 (*(volatile unsigned *)0x4F0000B0) //Bank5 write enable assertion delay control
#define rSMBCR0 (*(volatile unsigned *)0x4F000014) //Bank0 control
#define rSMBCR1 (*(volatile unsigned *)0x4F000034) //Bank1 control
#define rSMBCR2 (*(volatile unsigned *)0x4F000054) //Bank2 control
#define rSMBCR3 (*(volatile unsigned *)0x4F000074) //Bank3 control
#define rSMBCR4 (*(volatile unsigned *)0x4F000094) //Bank4 control
#define rSMBCR5 (*(volatile unsigned *)0x4F0000B4) //Bank5 control
#define rSMBSR0 (*(volatile unsigned *)0x4F000018) //Bank0 status
#define rSMBSR1 (*(volatile unsigned *)0x4F000038) //Bank1 status
#define rSMBSR2 (*(volatile unsigned *)0x4F000058) //Bank2 status
#define rSMBSR3 (*(volatile unsigned *)0x4F000078) //Bank3 status
#define rSMBSR4 (*(volatile unsigned *)0x4F000098) //Bank4 status
#define rSMBSR5 (*(volatile unsigned *)0x4F0000B8) //Bank5 status
#define rSMBWSTBRDR0 (*(volatile unsigned *)0x4F00001C) //Bank0 burst read wait delay control
#define rSMBWSTBRDR1 (*(volatile unsigned *)0x4F00003C) //Bank1 burst read wait delay control
#define rSMBWSTBRDR2 (*(volatile unsigned *)0x4F00005C) //Bank2 burst read wait delay control
#define rSMBWSTBRDR3 (*(volatile unsigned *)0x4F00007C) //Bank3 burst read wait delay control
#define rSMBWSTBRDR4 (*(volatile unsigned *)0x4F00009C) //Bank4 burst read wait delay control
#define rSMBWSTBRDR5 (*(volatile unsigned *)0x4F0000BC) //Bank5 burst read wait delay control
#define rSSMCSR (*(volatile unsigned *)0x4F000200) //SROMC status
#define rSSMCCR (*(volatile unsigned *)0x4F000204) //SROMC control
//chapter5 Nand Flash
#define rNFCONF (*(volatile unsigned *)0x4E000000) //NAND Flash configuration
#define rNFCONT (*(volatile unsigned *)0x4E000004) //NAND Flash control
#define rNFCMD (*(volatile unsigned *)0x4E000008) //NAND Flash command
#define rNFADDR (*(volatile unsigned *)0x4E00000C) //NAND Flash address
#define rNFDATA (*(volatile unsigned *)0x4E000010) //NAND Flash data
#define rNFDATA8 (*(volatile unsigned char *)0x4E000010) // NAND Flash data
#define NFDATA (0x4e000010)
#define rNFMECCD0 (*(volatile unsigned *)0x4E000014) //NAND Flash ECC for Main
#define rNFMECCD1 (*(volatile unsigned *)0x4E000018) //NAND Flash ECC for Main
#define rNFSECCD (*(volatile unsigned *)0x4E00001C) //NAND Flash ECC for Spare Area
#define rNFSBLK (*(volatile unsigned *)0x4E000020) //NAND Flash programmable start block address
#define rNFEBLK (*(volatile unsigned *)0x4E000024) //NAND Flash programmable end block address
#define rNFSTAT (*(volatile unsigned *)0x4E000028) //NAND Flash operation status
#define rNFECCERR0 (*(volatile unsigned *)0x4E00002C) //NAND Flash ECC Error Status for I/O [7:0]
#define rNFECCERR1 (*(volatile unsigned *)0x4E000030) //NAND Flash ECC Error Status for I/O [15:8]
#define rNFMECC0 (*(volatile unsigned *)0x4E000034) //SLC or MLC NAND Flash ECC status
#define rNFMECC1 (*(volatile unsigned *)0x4E000038) //SLC or MLC NAND Flash ECC status
#define rNFSECC (*(volatile unsigned *)0x4E00003C) //NAND Flash ECC for I/O[15:0]
#define rNFMLCBITPT (*(volatile unsigned *)0x4E000040) //NAND Flash 4-bit ECC Error Pattern for data[7:0]
//chapter6 SYSEM CONTROLLER
#define rLOCKTIME (*(volatile unsigned *)0x4C000000) //MPLL/UPLL lock time conuter
#define rMPLLCON (*(volatile unsigned *)0x4C000004) //MPLL configuration
#define rUPLLCON (*(volatile unsigned *)0x4C000008) //UPLL configuration
#define rCLKCON (*(volatile unsigned *)0x4C00000C) //Clock generator control
#define rCLKDIVN (*(volatile unsigned *)0x4C000014) //Clock divider control
#define rOSCSET (*(volatile unsigned *)0x4C000018) //Oscillator stabilization time counter
#define rCLKSRC (*(volatile unsigned *)0x4C00001C) //Clock source control
#define rPWRMODECON (*(volatile unsigned *)0x4C000020) //Power management mode setting
#define rPWRCFG (*(volatile unsigned *)0x4C000024) //Power management configuration
#define rWKUPSTAT (*(volatile unsigned *)0x4C000028) //Wakup status
#define rENDIAN (*(volatile unsigned *)0x4C00002C) //System endian control
#define rSWRSTCON (*(volatile unsigned *)0x4C000030) //S/W reset control
#define rRSTCON (*(volatile unsigned *)0x4C000034) //Reset control
#define rRSTSTAT (*(volatile unsigned *)0x4C000038) //Reset status
#define rINFORM0 (*(volatile unsigned *)0x4C000070) //User defined informtion
#define rINFORM1 (*(volatile unsigned *)0x4C000074) //User defined informtion
#define rINFORM2 (*(volatile unsigned *)0x4C000078) //User defined informtion
#define rINFORM3 (*(volatile unsigned *)0x4C00007C) //User defined informtion
#define rLOCKTIME (*(volatile unsigned *)0x4C000000) //MPLL/UPLL lock time count
#define rMPLLCON (*(volatile unsigned *)0x4C000004) //MPLL configuration
#define rUPLLCON (*(volatile unsigned *)0x4C000008) //UPLL configuration
#define rCLKCON (*(volatile unsigned *)0x4C00000C) //Clock generator control
#define rCLKDIVN (*(volatile unsigned *)0x4C000014) //Clock divider conrtrol
#define rCLKSRC (*(volatile unsigned *)0x4C00001C) //Clock source control
#define rOSCSET (*(volatile unsigned *)0x4C000018) //Oscillator stabilization control
#define rPWRMODECON (*(volatile unsigned *)0x4C000020) //Power manaement mode
#define rPWRCFG (*(volatile unsigned *)0x4C000024) //Power management configuration
#define rSWRSTCON (*(volatile unsigned *)0x4C000030) //sofrware reset control
#define rRSTCON (*(volatile unsigned *)0x4C000034) //Reset control
#define rWKUPSTAT (*(volatile unsigned *)0x4C000028) //Wakeup status
#define rRSTSTAT (*(volatile unsigned *)0x4C000038) //Reset status
#define rENDIAN (*(volatile unsigned *)0x4C00002C) //system endian configuration
#define rINFORM0 (*(volatile unsigned *)0x4C000070) //User defined information 0
#define rINFORM1 (*(volatile unsigned *)0x4C000074) //User defined information 1
#define rINFORM2 (*(volatile unsigned *)0x4C000078) //User defined information 2
#define rINFORM3 (*(volatile unsigned *)0x4C00007C) //User defined information 3
//chapter7 DMA
#define rDISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define rDISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define rDIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define rDCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
#define rDSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status (Read Only)
#define rDCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source (Read Only)
#define rDCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination (Read Only)
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
#define rDMAREQSEL0 (*(volatile unsigned *)0x4b000024) //DMA 0 Request Selection register
#define rDISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
#define rDISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
#define rDIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
#define rDIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
#define rDCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
#define rDSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status (Read Only)
#define rDCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source (Read Only)
#define rDCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination (Read Only)
#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
#define rDMAREQSEL1 (*(volatile unsigned *)0x4b000064) //DMA 1 Request Selection register
#define rDISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
#define rDISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
#define rDIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
#define rDIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
#define rDCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
#define rDSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status (Read Only)
#define rDCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source (Read Only)
#define rDCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination (Read Only)
#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
#define rDMAREQSEL2 (*(volatile unsigned *)0x4b0000a4) //DMA 2 Request Selection register
#define rDISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
#define rDISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
#define rDIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
#define rDIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
#define rDCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
#define rDSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status (Read Only)
#define rDCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source (Read Only)
#define rDCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination (Read Only)
#define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
#define rDMAREQSEL3 (*(volatile unsigned *)0x4b0000e4) //DMA 3 Request Selection register
//chapter8 I/O PORT
#define rGPACON (*(volatile unsigned *)0x56000000) //Configure the pins of port A
#define rGPADAT (*(volatile unsigned *)0x56000004) //The data for port A
#define rGPBCON (*(volatile unsigned *)0x56000010) //Configure the pins of port B
#define rGPBDAT (*(volatile unsigned *)0x56000014) //The data for port B
#define rGPBDN (*(volatile unsigned *)0x56000018) //Pull-down disable for port
#define rGPBSLPCON (*(volatile unsigned *)0x5600001C) //sleep mode configuration for port B
#define rGPCCON (*(volatile unsigned *)0x56000020) //Configure the pins of port C
#define rGPCDAT (*(volatile unsigned *)0x56000024) //The data for port C
#define rGPCDN (*(volatile unsigned *)0x56000028) //Pull-down disable for port C
#define rGPCSLPCON (*(volatile unsigned *)0x5600002C) //sleep mode configuration for port C
#define rGPDCON (*(volatile unsigned *)0x56000030) //Configure the pins of port D
#define rGPDDAT (*(volatile unsigned *)0x56000034) //The data for port D
#define rGPDDN (*(volatile unsigned *)0x56000038) //Pull-down disable for port D
#define rGPDSLPCON (*(volatile unsigned *)0x5600003C) //sleep mode configuration for port D
#define rGPECON (*(volatile unsigned *)0x56000040) //Configure the pins of port E
#define rGPEDAT (*(volatile unsigned *)0x56000044) //The data for port E
#define rGPEDN (*(volatile unsigned *)0x56000048) //Pull-down disable for port E
#define rGPESLPCON (*(volatile unsigned *)0x5600004C) //sleep mode configuration for port E
#define rGPFCON (*(volatile unsigned *)0x56000050) //Configure the pins of port F
#define rGPFDAT (*(volatile unsigned *)0x56000054) //The data for port F
#define rGPFDN (*(volatile unsigned *)0x56000058) //Pull-down disable for port F
#define rGPGCON (*(volatile unsigned *)0x56000060) //Configure the pins of portt G
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