//   </e>
        XM2CON_Val      EQU     0x00000000
        XM2PAR_Val      EQU     0x000070FF

//   <e.0>  Enable Memory Region 3
//     <o.1>       Data Bus Width  <0=> 8-bit  <1=> 16-bit
//     <o1.11>     Byte Address Mode Forced
//     <o1.15>     Byte Enabled Write Strobe
//     <o1.10>     Disable extra Address Latch Hold Cycle
//     <o1.8>      Disable extra Write Address Hold Cycle
//     <o1.9>      Disable Read Bus Turn Cycle
//     <o1.12..14> Address Wait States <0-7>
//                 <i> Number of Wait States added for AE
//     <o1.0..3>   Read Wait States <0-15>
//                 <i> Number of Wait States added for RS
//     <o1.4..7>   Write Wait States <0-15>
//                 <i> Number of Wait States added for WS
//   </e>
        XM3CON_Val      EQU     0x00000000
        XM3PAR_Val      EQU     0x000070FF

//   <e.0>         Memory Muxed Mode
        XMCFG_Val       EQU     0x00000001
//   </e>

// </e>


$IF (RAM_INTVEC)
// Exception Vector Area in RAM
AREA   VECTORS, DATA, AT 0x00010000
                DS      64
$ENDIF        
        

// Startup Code must be linked at address which it expects to run.
									
AREA   STARTUPCODE, CODE, AT 0x00080000
       PUBLIC  __startup

       EXTERN  CODE32 (?C?INIT)

__startup       PROC    CODE32

// Pre-defined interrupt handlers that may be directly 
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (SWI_Handler?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)

// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.

Vectors:        LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                NOP                            /* Reserved Vector */
                LDR     PC,IRQ_Addr
                LDR     PC,FIQ_Addr

Reset_Addr:     DD      Reset_Handler
Undef_Addr:     DD      Undef_Handler?A
SWI_Addr:       DD      SWI_Handler?A
PAbt_Addr:      DD      PAbt_Handler?A
DAbt_Addr:      DD      DAbt_Handler?A
                DD      0                      /* Reserved Address */
IRQ_Addr:       DD      IRQ_Handler?A
FIQ_Addr:       DD      FIQ_Handler?A


// Reset Handler

Reset_Handler:  


// Setup PLL
IF (PLL_SETUP != 0)
                LDR     R0, =MMR_BASE
                MOV     R1, #0x01         
                STR     R1, [R0,#POWKEY1_OFFSET]          
                MOV     R1, #PLLCFG_Val      
                STR     R1, [R0,#POWCON_OFFSET]    
                MOV     R1, #0xF4
                STR     R1, [R0,#POWKEY2_OFFSET]
ENDIF   ; PLL_SETUP


// Setup Pins
IF (GPIO_SETUP != 0)

                ADR     R10, GPIO_CFG          /* Pointer to GPIO CFG */
                LDMIA   R10, {R0-R5}           /* Load GPIO Configuration */
                STMIA   R0, {R1-R5}            /* Store GPxCON */
                B       GPIO_END

GPIO_CFG:       DD      GPIOBASE
                DD      GP0CON_Val
                DD      GP1CON_Val
                DD      GP2CON_Val
                DD      GP3CON_Val
                DD      GP4CON_Val
GPIO_END:

ENDIF   ; GPIO_SETUP


// Setup External Memory Interface
IF (XM_SETUP != 0)

                ADR     R10, XM_CFG            /* Pointer to XM CFG */
                LDMIA   R10, {R0-R9}           /* Load XM Configuration */
                STR     R1, [R0],#0x10         /* Store XMCFG */
                STMIA   R0, {R2-R9}            /* Store XMxCON & XMxPAR */
                B       XM_END

XM_CFG:         DD      XMBASE
                DD      XMCFG_Val
                DD      XM0CON_Val
                DD      XM1CON_Val
                DD      XM2CON_Val
                DD      XM3CON_Val
                DD      XM0PAR_Val
                DD      XM1PAR_Val
                DD      XM2PAR_Val
                DD      XM3PAR_Val
XM_END:

ENDIF   ; XM_SETUP


// Copy Exception Vectors to Internal RAM and Remap Memory
//  (when Interrupt Vectors are in RAM)

$IF (RAM_INTVEC)
                ADR     R8, Vectors         ; Source
                LDR     R9, =0x00010000     ; Destination
                LDMIA   R8!, {R0-R7}        ; Load Vectors 
                STMIA   R9!, {R0-R7}        ; Store Vectors 
                LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
                STMIA   R9!, {R0-R7}        ; Store Handler Addresses 
                LDR     R0, =MMR_BASE
                MOV     R1, #1     
                STR     R1, [R0,#PREMAP_OFFSET]          
                STR     R1, [R0,#REMAP_OFFSET]          
$ENDIF


// Setup Stack for each mode
                LDR     R0, =Top_Stack

// Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

// Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

// Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

// Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

// Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

// Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                MOV     SP, R0

// Enter the C code
                LDR     R0,=?C?INIT
                TST     R0,#1       ; Bit-0 set: main is Thumb
                LDREQ   LR,=exit?A  ; ARM Mode
                LDRNE   LR,=exit?T  ; Thumb Mode
                BX      R0
                ENDP

PUBLIC exit?A
exit?A          PROC    CODE32
                B       exit?A
                ENDP

PUBLIC exit?T
exit?T          PROC    CODE16
                B       exit?T
                ENDP

                END