?? dec2812.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "A\[9\] " "Info: Assuming node \"A\[9\]\" is an undefined clock" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "A\[9\]" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A\[10\] " "Info: Assuming node \"A\[10\]\" is an undefined clock" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "A\[10\]" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 208 88 256 224 "WR" "" } { 1696 792 824 1712 "WR" "" } { 1904 104 136 1920 "WR" "" } { 1904 368 400 1920 "WR" "" } { 1904 792 824 1920 "WR" "" } { 1440 560 592 1456 "WR" "" } { 2120 904 936 2136 "WR" "" } { 2344 120 200 2360 "WR" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A\[12\] " "Info: Assuming node \"A\[12\]\" is an undefined clock" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "A\[12\]" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "A\[11\] " "Info: Assuming node \"A\[11\]\" is an undefined clock" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 456 88 256 472 "A\[12..9\]" "" } { 944 96 129 960 "A\[12\]" "" } { 960 96 184 976 "A\[10\]" "" } { 976 96 184 992 "A\[11\]" "" } { 992 96 184 1008 "A\[9\]" "" } { 1192 96 184 1208 "A\[9\]" "" } { 1176 96 136 1192 "A\[10\]" "" } { 1160 96 136 1176 "A\[11\]" "" } { 1144 96 184 1160 "A\[12\]" "" } { 1392 96 184 1408 "A\[9\]" "" } { 1344 96 136 1360 "A\[12\]" "" } { 1360 96 184 1376 "A\[11\]" "" } { 1376 96 184 1392 "A\[10\]" "" } { 1560 360 448 1576 "A\[12\]" "" } { 1608 360 400 1624 "A\[9\]" "" } { 1560 792 872 1576 "A\[12\]" "" } { 1576 792 872 1592 "A\[11\]" "" } { 1592 792 872 1608 "A\[10\]" "" } { 1608 792 872 1624 "A\[9\]" "" } { 1768 104 184 1784 "A\[12\]" "" } { 1784 104 184 1800 "A\[11\]" "" } { 1800 104 184 1816 "A\[10\]" "" } { 1816 104 136 1832 "A\[9\]" "" } { 1768 368 448 1784 "A\[12\]" "" } { 1784 368 448 1800 "A\[11\]" "" } { 1816 368 448 1832 "A\[9\]" "" } { 1608 96 184 1624 "A\[9\]" "" } { 1560 96 184 1576 "A\[12\]" "" } { 1576 96 136 1592 "A\[11\]" "" } { 1800 368 401 1816 "A\[10\]" "" } { 1768 792 825 1784 "A\[12\]" "" } { 1784 792 825 1800 "A\[11\]" "" } { 1800 792 872 1816 "A\[10\]" "" } { 1816 792 872 1832 "A\[9\]" "" } { 1304 560 640 1320 "A\[12\]" "" } { 1336 560 640 1352 "A\[10\]" "" } { 1352 560 640 1368 "A\[9\]" "" } { 1320 560 593 1336 "A\[11\]" "" } { 1592 360 448 1608 "A\[10\]" "" } { 1576 360 400 1592 "A\[11\]" "" } { 1592 96 136 1608 "A\[10\]" "" } { 1256 792 825 1272 "A\[11\]" "" } { 1288 792 872 1304 "A\[9\]" "" } { 1240 792 872 1256 "A\[12\]" "" } { 1272 792 872 1288 "A\[10\]" "" } { 1416 792 872 1432 "A\[11\]" "" } { 1400 792 825 1416 "A\[12\]" "" } { 1432 792 825 1448 "A\[10\]" "" } { 1448 792 872 1464 "A\[9\]" "" } { 1984 904 984 2000 "A\[12\]" "" } { 2000 904 984 2016 "A\[11\]" "" } { 2032 904 984 2048 "A\[9\]" "" } { 2016 904 937 2032 "A\[10\]" "" } { 2208 200 280 2224 "A\[12\]" "" } { 2224 200 280 2240 "A\[11\]" "" } { 2240 120 224 2256 "A\[10\]" "" } { 2256 120 168 2272 "A\[9\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "A\[11\]" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst39 " "Info: Detected gated clock \"inst39\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1680 872 936 1728 "inst39" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst39" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst42 " "Info: Detected gated clock \"inst42\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 184 248 1936 "inst42" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst42" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst73~29 " "Info: Detected gated clock \"inst73~29\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2304 296 360 2352 "inst73" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst73~29" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst62~17 " "Info: Detected gated clock \"inst62~17\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2104 984 1048 2152 "inst62" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst62~17" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst62 " "Info: Detected gated clock \"inst62\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2104 984 1048 2152 "inst62" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst62" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst50 " "Info: Detected gated clock \"inst50\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 872 936 1936 "inst50" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst50" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst55 " "Info: Detected gated clock \"inst55\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1424 640 704 1472 "inst55" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst55" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst50~22 " "Info: Detected gated clock \"inst50~22\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 872 936 1936 "inst50" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst50~22" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "inst46 " "Info: Detected gated clock \"inst46\" as buffer" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1888 448 512 1936 "inst46" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst46" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A\[9\] " "Info: No valid register-to-register data paths exist for clock \"A\[9\]\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "A\[10\] " "Info: No valid register-to-register data paths exist for clock \"A\[10\]\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WR " "Info: No valid register-to-register data paths exist for clock \"WR\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
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