?? dec2812.fit.qmsg
字號:
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.399 ns register pin " "Info: Estimated most critical path is register to pin delay of 5.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74273:inst7\|18 1 REG LAB_X7_Y1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y1; Fanout = 4; REG Node = '74273:inst7\|18'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { 74273:inst7|18 } "NODE_NAME" } "" } } { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { 168 320 384 248 "18" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.914 ns) 1.357 ns 74138:inst10\|15 2 COMB LAB_X7_Y1 1 " "Info: 2: + IC(0.443 ns) + CELL(0.914 ns) = 1.357 ns; Loc. = LAB_X7_Y1; Fanout = 1; COMB Node = '74138:inst10\|15'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "1.357 ns" { 74273:inst7|18 74138:inst10|15 } "NODE_NAME" } "" } } { "74138.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74138.bdf" { { 16 568 632 88 "15" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.720 ns) + CELL(2.322 ns) 5.399 ns CE\[0\] 3 PIN PIN_57 0 " "Info: 3: + IC(1.720 ns) + CELL(2.322 ns) = 5.399 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'CE\[0\]'" { } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "4.042 ns" { 74138:inst10|15 CE[0] } "NODE_NAME" } "" } } { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 1120 808 984 1136 "CE\[3..0\]" "" } { 808 920 956 824 "CE\[0\]" "" } { 824 920 956 840 "CE\[1\]" "" } { 840 920 956 856 "CE\[2\]" "" } { 856 920 956 872 "CE\[3\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 59.94 % ) " "Info: Total cell delay = 3.236 ns ( 59.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.163 ns ( 40.06 % ) " "Info: Total interconnect delay = 2.163 ns ( 40.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "5.399 ns" { 74273:inst7|18 74138:inst10|15 CE[0] } "NODE_NAME" } "" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "10 10 " "Info: Average interconnect usage is 10% of the available device resources. Peak interconnect usage is 10%" { } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." { } { } 0 0 "The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "74244:inst13\|26~42 " "Info: Following pins have the same output enable: 74244:inst13\|26~42" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[7\] LVTTL " "Info: Type bidirectional pin D\[7\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[7\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[7] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[7] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[6\] LVTTL " "Info: Type bidirectional pin D\[6\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[6\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[6] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[6] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[5\] LVTTL " "Info: Type bidirectional pin D\[5\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[5\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[5] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[5] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[4\] LVTTL " "Info: Type bidirectional pin D\[4\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[4\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[4] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[4] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[3\] LVTTL " "Info: Type bidirectional pin D\[3\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[3\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[3] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[3] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[2\] LVTTL " "Info: Type bidirectional pin D\[2\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[2\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[2] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[2] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[1\] LVTTL " "Info: Type bidirectional pin D\[1\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[1\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[1] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[1] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional D\[0\] LVTTL " "Info: Type bidirectional pin D\[0\] uses the LVTTL I/O standard" { } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 128 80 256 144 "D\[7..0\]" "" } { 192 328 360 208 "D\[7\]" "" } { 176 328 360 192 "D\[6\]" "" } { 160 328 360 176 "D\[5\]" "" } { 144 328 360 160 "D\[4\]" "" } { 112 328 360 128 "D\[3\]" "" } { 96 328 360 112 "D\[2\]" "" } { 80 328 360 96 "D\[1\]" "" } { 64 328 360 80 "D\[0\]" "" } { 304 328 360 320 "D\[0\]" "" } { 320 328 360 336 "D\[1\]" "" } { 336 328 360 352 "D\[2\]" "" } { 352 328 360 368 "D\[3\]" "" } { 384 328 360 400 "D\[4\]" "" } { 400 328 360 416 "D\[5\]" "" } { 416 328 360 432 "D\[6\]" "" } { 432 328 360 448 "D\[7\]" "" } { 544 328 360 560 "D\[0\]" "" } { 560 328 360 576 "D\[1\]" "" } { 576 328 360 592 "D\[2\]" "" } { 592 328 360 608 "D\[3\]" "" } { 624 328 360 640 "D\[4\]" "" } { 640 328 360 656 "D\[5\]" "" } { 656 328 360 672 "D\[6\]" "" } { 672 328 360 688 "D\[7\]" "" } { 824 328 360 840 "D\[0\]" "" } { 840 328 360 856 "D\[1\]" "" } { 856 328 360 872 "D\[2\]" "" } { 872 328 360 888 "D\[3\]" "" } { 904 328 360 920 "D\[4\]" "" } { 920 328 360 936 "D\[5\]" "" } { 936 328 360 952 "D\[6\]" "" } { 952 328 360 968 "D\[7\]" "" } { 1072 328 360 1088 "D\[0\]" "" } { 1088 328 360 1104 "D\[1\]" "" } { 1104 328 360 1120 "D\[2\]" "" } { 1120 328 360 1136 "D\[3\]" "" } { 1152 328 360 1168 "D\[4\]" "" } { 1168 328 360 1184 "D\[5\]" "" } { 1184 328 360 1200 "D\[6\]" "" } { 1200 328 360 1216 "D\[7\]" "" } { 1336 328 360 1352 "D\[0\]" "" } { 1352 328 360 1368 "D\[1\]" "" } { 1368 328 360 1384 "D\[2\]" "" } { 1384 328 360 1400 "D\[3\]" "" } { 1416 328 360 1432 "D\[4\]" "" } { 1432 328 360 1448 "D\[5\]" "" } { 1448 328 360 1464 "D\[6\]" "" } { 1464 328 360 1480 "D\[7\]" "" } } } } { "f:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "D\[0\]" } } } } { "f:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "f:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DEC2812" "UNKNOWN" "V1" "D:/2812board_N/db/DEC2812.quartus_db" { Floorplan "D:/2812board_N/" "" "" { D[0] } "NODE_NAME" } "" } } { "D:/2812board_N/DEC2812.fld" "" { Floorplan "D:/2812board_N/DEC2812.fld" "" "" { D[0] } "NODE_NAME" } } } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} } { } 0 0 "Following pins have the same output enable: %1!s!" 0 0} } { } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 26 16:59:48 2007 " "Info: Processing ended: Thu Jul 26 16:59:48 2007" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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