; N/A           ; None        ; 3.648 ns  ; D[2] ; 74273:inst22|17 ; WR       ;
; N/A           ; None        ; 3.580 ns  ; D[1] ; 74273:inst1|18  ; WR       ;
; N/A           ; None        ; 3.579 ns  ; D[4] ; 74273:inst2|15  ; A[9]     ;
; N/A           ; None        ; 3.540 ns  ; D[7] ; 74273:inst|12   ; A[11]    ;
; N/A           ; None        ; 3.509 ns  ; D[4] ; 74273:inst1|15  ; A[12]    ;
; N/A           ; None        ; 3.477 ns  ; D[6] ; 74273:inst|13   ; A[11]    ;
; N/A           ; None        ; 3.437 ns  ; D[3] ; 74273:inst1|16  ; A[12]    ;
; N/A           ; None        ; 3.437 ns  ; D[0] ; 74273:inst1|19  ; A[12]    ;
; N/A           ; None        ; 3.431 ns  ; D[7] ; 74273:inst1|12  ; A[9]     ;
; N/A           ; None        ; 3.398 ns  ; D[5] ; 74273:inst|14   ; A[11]    ;
; N/A           ; None        ; 3.398 ns  ; D[1] ; 74273:inst7|18  ; WR       ;
; N/A           ; None        ; 3.397 ns  ; D[7] ; 74273:inst|12   ; A[9]     ;
; N/A           ; None        ; 3.376 ns  ; D[3] ; 74273:inst2|16  ; A[9]     ;
; N/A           ; None        ; 3.368 ns  ; D[4] ; 74273:inst2|15  ; A[10]    ;
; N/A           ; None        ; 3.349 ns  ; D[4] ; 74273:inst|15   ; A[11]    ;
; N/A           ; None        ; 3.334 ns  ; D[6] ; 74273:inst|13   ; A[9]     ;
; N/A           ; None        ; 3.322 ns  ; D[3] ; 74273:inst|16   ; A[11]    ;
; N/A           ; None        ; 3.315 ns  ; D[5] ; 74273:inst2|14  ; A[9]     ;
; N/A           ; None        ; 3.313 ns  ; D[1] ; 74273:inst22|18 ; A[9]     ;
; N/A           ; None        ; 3.286 ns  ; D[0] ; 74273:inst|19   ; A[11]    ;
; N/A           ; None        ; 3.279 ns  ; D[2] ; 74273:inst1|17  ; A[12]    ;
; N/A           ; None        ; 3.272 ns  ; D[4] ; 74273:inst2|15  ; A[11]    ;
; N/A           ; None        ; 3.267 ns  ; D[1] ; 74273:inst7|18  ; A[12]    ;
; N/A           ; None        ; 3.255 ns  ; D[5] ; 74273:inst|14   ; A[9]     ;
; N/A           ; None        ; 3.246 ns  ; D[4] ; 74273:inst1|15  ; A[9]     ;
; N/A           ; None        ; 3.224 ns  ; D[2] ; 74273:inst|17   ; A[11]    ;
; N/A           ; None        ; 3.206 ns  ; D[4] ; 74273:inst|15   ; A[9]     ;
; N/A           ; None        ; 3.197 ns  ; D[1] ; 74273:inst|18   ; A[11]    ;
; N/A           ; None        ; 3.190 ns  ; D[7] ; 74273:inst|12   ; A[10]    ;
; N/A           ; None        ; 3.179 ns  ; D[3] ; 74273:inst|16   ; A[9]     ;
; N/A           ; None        ; 3.174 ns  ; D[6] ; 74273:inst2|13  ; A[9]     ;
; N/A           ; None        ; 3.174 ns  ; D[3] ; 74273:inst1|16  ; A[9]     ;
; N/A           ; None        ; 3.174 ns  ; D[0] ; 74273:inst1|19  ; A[9]     ;
; N/A           ; None        ; 3.172 ns  ; D[1] ; 74273:inst22|18 ; A[12]    ;
; N/A           ; None        ; 3.165 ns  ; D[3] ; 74273:inst2|16  ; A[10]    ;
; N/A           ; None        ; 3.143 ns  ; D[0] ; 74273:inst|19   ; A[9]     ;
; N/A           ; None        ; 3.127 ns  ; D[6] ; 74273:inst|13   ; A[10]    ;
; N/A           ; None        ; 3.105 ns  ; D[6] ; 74273:inst1|13  ; A[12]    ;
; N/A           ; None        ; 3.104 ns  ; D[5] ; 74273:inst2|14  ; A[10]    ;
; N/A           ; None        ; 3.087 ns  ; D[0] ; 74273:inst2|19  ; A[9]     ;
; N/A           ; None        ; 3.081 ns  ; D[2] ; 74273:inst|17   ; A[9]     ;
; N/A           ; None        ; 3.077 ns  ; D[5] ; 74273:inst1|14  ; A[12]    ;
; N/A           ; None        ; 3.069 ns  ; D[3] ; 74273:inst2|16  ; A[11]    ;
; N/A           ; None        ; 3.054 ns  ; D[1] ; 74273:inst|18   ; A[9]     ;
; N/A           ; None        ; 3.052 ns  ; D[1] ; 74273:inst2|18  ; A[9]     ;
; N/A           ; None        ; 3.048 ns  ; D[5] ; 74273:inst|14   ; A[10]    ;
; N/A           ; None        ; 3.034 ns  ; D[2] ; 74273:inst22|17 ; A[9]     ;
; N/A           ; None        ; 3.017 ns  ; D[7] ; 74273:inst1|12  ; A[10]    ;
; N/A           ; None        ; 3.016 ns  ; D[2] ; 74273:inst1|17  ; A[9]     ;
; N/A           ; None        ; 3.008 ns  ; D[5] ; 74273:inst2|14  ; A[11]    ;
; N/A           ; None        ; 2.999 ns  ; D[4] ; 74273:inst|15   ; A[10]    ;
; N/A           ; None        ; 2.993 ns  ; D[7] ; 74273:inst1|12  ; A[11]    ;
; N/A           ; None        ; 2.972 ns  ; D[3] ; 74273:inst|16   ; A[10]    ;
; N/A           ; None        ; 2.966 ns  ; D[2] ; 74273:inst2|17  ; A[9]     ;
; N/A           ; None        ; 2.963 ns  ; D[6] ; 74273:inst2|13  ; A[10]    ;
; N/A           ; None        ; 2.936 ns  ; D[0] ; 74273:inst|19   ; A[10]    ;
; N/A           ; None        ; 2.932 ns  ; D[0] ; 74273:inst11|19 ; A[12]    ;
; N/A           ; None        ; 2.899 ns  ; D[1] ; 74273:inst22|18 ; A[10]    ;
; N/A           ; None        ; 2.893 ns  ; D[2] ; 74273:inst22|17 ; A[12]    ;
; N/A           ; None        ; 2.876 ns  ; D[0] ; 74273:inst2|19  ; A[10]    ;
; N/A           ; None        ; 2.874 ns  ; D[2] ; 74273:inst|17   ; A[10]    ;
; N/A           ; None        ; 2.867 ns  ; D[6] ; 74273:inst2|13  ; A[11]    ;
; N/A           ; None        ; 2.847 ns  ; D[1] ; 74273:inst|18   ; A[10]    ;
; N/A           ; None        ; 2.842 ns  ; D[6] ; 74273:inst1|13  ; A[9]     ;
; N/A           ; None        ; 2.841 ns  ; D[1] ; 74273:inst2|18  ; A[10]    ;
; N/A           ; None        ; 2.832 ns  ; D[4] ; 74273:inst1|15  ; A[10]    ;
; N/A           ; None        ; 2.822 ns  ; D[1] ; 74273:inst1|18  ; A[12]    ;
; N/A           ; None        ; 2.814 ns  ; D[5] ; 74273:inst1|14  ; A[9]     ;
; N/A           ; None        ; 2.813 ns  ; D[0] ; 74273:inst22|19 ; WR       ;
; N/A           ; None        ; 2.808 ns  ; D[4] ; 74273:inst1|15  ; A[11]    ;
; N/A           ; None        ; 2.780 ns  ; D[0] ; 74273:inst2|19  ; A[11]    ;
; N/A           ; None        ; 2.760 ns  ; D[3] ; 74273:inst1|16  ; A[10]    ;
; N/A           ; None        ; 2.760 ns  ; D[0] ; 74273:inst1|19  ; A[10]    ;
; N/A           ; None        ; 2.755 ns  ; D[2] ; 74273:inst2|17  ; A[10]    ;
; N/A           ; None        ; 2.745 ns  ; D[1] ; 74273:inst2|18  ; A[11]    ;
; N/A           ; None        ; 2.736 ns  ; D[3] ; 74273:inst1|16  ; A[11]    ;
; N/A           ; None        ; 2.736 ns  ; D[0] ; 74273:inst1|19  ; A[11]    ;
; N/A           ; None        ; 2.674 ns  ; D[0] ; 74273:inst11|19 ; A[9]     ;
; N/A           ; None        ; 2.671 ns  ; D[0] ; 74273:inst7|19  ; A[11]    ;
; N/A           ; None        ; 2.659 ns  ; D[2] ; 74273:inst2|17  ; A[11]    ;
; N/A           ; None        ; 2.620 ns  ; D[2] ; 74273:inst22|17 ; A[10]    ;
; N/A           ; None        ; 2.602 ns  ; D[2] ; 74273:inst1|17  ; A[10]    ;
; N/A           ; None        ; 2.578 ns  ; D[2] ; 74273:inst1|17  ; A[11]    ;
; N/A           ; None        ; 2.559 ns  ; D[1] ; 74273:inst1|18  ; A[9]     ;
; N/A           ; None        ; 2.537 ns  ; D[0] ; 74273:inst7|19  ; A[9]     ;
; N/A           ; None        ; 2.512 ns  ; D[2] ; 74273:inst7|17  ; A[11]    ;
; N/A           ; None        ; 2.468 ns  ; D[1] ; 74273:inst22|18 ; A[11]    ;
; N/A           ; None        ; 2.428 ns  ; D[6] ; 74273:inst1|13  ; A[10]    ;
; N/A           ; None        ; 2.404 ns  ; D[6] ; 74273:inst1|13  ; A[11]    ;
; N/A           ; None        ; 2.400 ns  ; D[5] ; 74273:inst1|14  ; A[10]    ;
; N/A           ; None        ; 2.378 ns  ; D[2] ; 74273:inst7|17  ; A[9]     ;
; N/A           ; None        ; 2.376 ns  ; D[5] ; 74273:inst1|14  ; A[11]    ;
; N/A           ; None        ; 2.326 ns  ; D[0] ; 74273:inst7|19  ; A[10]    ;
; N/A           ; None        ; 2.255 ns  ; D[0] ; 74273:inst11|19 ; A[10]    ;
; N/A           ; None        ; 2.229 ns  ; D[0] ; 74273:inst11|19 ; A[11]    ;
; N/A           ; None        ; 2.199 ns  ; D[0] ; 74273:inst22|19 ; A[9]     ;
; N/A           ; None        ; 2.189 ns  ; D[2] ; 74273:inst22|17 ; A[11]    ;
; N/A           ; None        ; 2.167 ns  ; D[2] ; 74273:inst7|17  ; A[10]    ;
; N/A           ; None        ; 2.145 ns  ; D[1] ; 74273:inst1|18  ; A[10]    ;
; N/A           ; None        ; 2.121 ns  ; D[1] ; 74273:inst1|18  ; A[11]    ;
; N/A           ; None        ; 2.058 ns  ; D[0] ; 74273:inst22|19 ; A[12]    ;
; N/A           ; None        ; 2.024 ns  ; D[1] ; 74273:inst7|18  ; A[11]    ;
; N/A           ; None        ; 1.890 ns  ; D[1] ; 74273:inst7|18  ; A[9]     ;
; N/A           ; None        ; 1.785 ns  ; D[0] ; 74273:inst22|19 ; A[10]    ;
; N/A           ; None        ; 1.679 ns  ; D[1] ; 74273:inst7|18  ; A[10]    ;
; N/A           ; None        ; 1.354 ns  ; D[0] ; 74273:inst22|19 ; A[11]    ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Jul 26 16:59:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DEC2812 -c DEC2812
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "A[9]" is an undefined clock
    Info: Assuming node "A[10]" is an undefined clock
    Info: Assuming node "WR" is an undefined clock
    Info: Assuming node "A[12]" is an undefined clock
    Info: Assuming node "A[11]" is an undefined clock
Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "inst39" as buffer
    Info: Detected gated clock "inst42" as buffer
    Info: Detected gated clock "inst73~29" as buffer
    Info: Detected gated clock "inst62~17" as buffer
    Info: Detected gated clock "inst62" as buffer
    Info: Detected gated clock "inst50" as buffer
    Info: Detected gated clock "inst55" as buffer
    Info: Detected gated clock "inst50~22" as buffer
    Info: Detected gated clock "inst46" as buffer
Info: No valid register-to-register data paths exist for clock "A[9]"
Info: No valid register-to-register data paths exist for clock "A[10]"
Info: No valid register-to-register data paths exist for clock "WR"
Info: No valid register-to-register data paths exist for clock "A[12]"
Info: No valid register-to-register data paths exist for clock "A[11]"
Info: tsu for register "74273:inst22|19" (data pin = "D[0]", clock pin = "A[11]") is -0.800 ns
    Info: + Longest pin to register delay is 3.748 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_99; Fanout = 1; PIN Node = 'D[0]'
        Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X2_Y5_N1; Fanout = 6; COMB Node = 'D~7'
        Info: 3: + IC(2.336 ns) + CELL(0.280 ns) = 3.748 ns; Loc. = LC_X2_Y3_N7; Fanout = 1; REG Node = '74273:inst22|19'
        Info: Total cell delay = 1.412 ns ( 37.67 % )
        Info: Total interconnect delay = 2.336 ns ( 62.33 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "A[11]" to destination register is 4.881 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'A[11]'
        Info: 2: + IC(1.381 ns) + CELL(0.740 ns) = 3.284 ns; Loc. = LC_X2_Y3_N3; Fanout = 3; COMB Node = 'inst62'
        Info: 3: + IC(0.679 ns) + CELL(0.918 ns) = 4.881 ns; Loc. = LC_X2_Y3_N7; Fanout = 1; REG Node = '74273:inst22|19'
        Info: Total cell delay = 2.821 ns ( 57.80 % )
        Info: Total interconnect delay = 2.060 ns ( 42.20 % )
Info: tco from clock "WR" to destination pin "CE[0]" through register "74273:inst7|18" is 14.717 ns
    Info: + Longest clock path from clock "WR" to source register is 8.563 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 5; CLK Node = 'WR'
        Info: 2: + IC(2.253 ns) + CELL(0.740 ns) = 4.125 ns; Loc. = LC_X2_Y3_N8; Fanout = 3; COMB Node = 'inst50~22'
        Info: 3: + IC(0.742 ns) + CELL(0.200 ns) = 5.067 ns; Loc. = LC_X2_Y3_N4; Fanout = 3; COMB Node = 'inst50'
        Info: 4: + IC(2.578 ns) + CELL(0.918 ns) = 8.563 ns; Loc. = LC_X7_Y1_N4; Fanout = 4; REG Node = '74273:inst7|18'
        Info: Total cell delay = 2.990 ns ( 34.92 % )
        Info: Total interconnect delay = 5.573 ns ( 65.08 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.778 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 4; REG Node = '74273:inst7|18'
        Info: 2: + IC(0.986 ns) + CELL(0.511 ns) = 1.497 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; COMB Node = '74138:inst10|15'
        Info: 3: + IC(1.959 ns) + CELL(2.322 ns) = 5.778 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'CE[0]'
        Info: Total cell delay = 2.833 ns ( 49.03 % )
        Info: Total interconnect delay = 2.945 ns ( 50.97 % )
Info: Longest tpd from source pin "A[11]" to destination pin "D[1]" is 12.021 ns
    Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'A[11]'
    Info: 2: + IC(3.128 ns) + CELL(0.914 ns) = 5.205 ns; Loc. = LC_X2_Y2_N5; Fanout = 3; COMB Node = 'inst76~27'
    Info: 3: + IC(0.784 ns) + CELL(0.511 ns) = 6.500 ns; Loc. = LC_X2_Y2_N1; Fanout = 2; COMB Node = 'inst77'
    Info: 4: + IC(2.043 ns) + CELL(0.511 ns) = 9.054 ns; Loc. = LC_X2_Y4_N1; Fanout = 1; COMB Node = '74244:inst13|6~120'
    Info: 5: + IC(0.645 ns) + CELL(2.322 ns) = 12.021 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'D[1]'
    Info: Total cell delay = 5.421 ns ( 45.10 % )
    Info: Total interconnect delay = 6.600 ns ( 54.90 % )
Info: th for register "74273:inst|12" (data pin = "D[7]", clock pin = "WR") is 4.914 ns
    Info: + Longest clock path from clock "WR" to destination register is 9.177 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_96; Fanout = 5; CLK Node = 'WR'
        Info: 2: + IC(2.253 ns) + CELL(0.740 ns) = 4.125 ns; Loc. = LC_X2_Y3_N8; Fanout = 3; COMB Node = 'inst50~22'
        Info: 3: + IC(0.745 ns) + CELL(0.200 ns) = 5.070 ns; Loc. = LC_X2_Y3_N0; Fanout = 8; COMB Node = 'inst39'
        Info: 4: + IC(3.189 ns) + CELL(0.918 ns) = 9.177 ns; Loc. = LC_X7_Y4_N8; Fanout = 1; REG Node = '74273:inst|12'
        Info: Total cell delay = 2.990 ns ( 32.58 % )
        Info: Total interconnect delay = 6.187 ns ( 67.42 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 4.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_6; Fanout = 1; PIN Node = 'D[7]'
        Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X1_Y3_N0; Fanout = 2; COMB Node = 'D~0'
        Info: 3: + IC(3.072 ns) + CELL(0.280 ns) = 4.484 ns; Loc. = LC_X7_Y4_N8; Fanout = 1; REG Node = '74273:inst|12'
        Info: Total cell delay = 1.412 ns ( 31.49 % )
        Info: Total interconnect delay = 3.072 ns ( 68.51 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Jul 26 16:59:52 2007
    Info: Elapsed time: 00:00:01