//  ----------------------------------------------------------------------------
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
//  ----------------------------------------------------------------------------
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//  ----------------------------------------------------------------------------
//* File Name           : NandFlash.h
//* Object              : NandFlash constant description
//* Creation            : NLe  26/Apr/2005
//*
//*----------------------------------------------------------------------------
#ifndef NandFlash_h
#define NandFlash_h

#define CFG_MAX_NAND_DEVICE            1	/* Max number of NAND devices		*/
#define NANDFLASH_PAGESIZE	           512
#define SECTORSIZE                     512
#define AT91_SMARTMEDIA_BASE           0x40000000

#define ADDR_COLUMN                    1
#define ADDR_PAGE                      2
#define ADDR_COLUMN_PAGE               3

#define NAND_ChipID_UNKNOWN	       	   0
#define NAND_MAX_FLOORS                1
#define NAND_MAX_CHIPS                 1

#define AT91_SMART_MEDIA_ALE           (1 << 22)	/* our ALE is AD22 */
#define AT91_SMART_MEDIA_CLE           (1 << 21)	/* our CLE is AD21 */

// SMC Chip Select 3 Timings for NandFlash K9F1216U0A (samsung)
// for AT91C_MASTER_CLOCK = 48000000. They were generated according to 
// K9F1216U0A timings and for AT91C_MASTER_CLOCK = 48000000.
// Please refer to SMC section in AT91SAM9261 datasheet to learn how 
// to generate these values.
#define AT91C_SM_NWE_SETUP		(0 << 0)		
#define AT91C_SM_NCS_WR_SETUP	(0 << 8)		
#define AT91C_SM_NRD_SETUP		(0 << 16)		
#define AT91C_SM_NCS_RD_SETUP	(0 << 24)		
  
#define AT91C_SM_NWE_PULSE 		(2 << 0)		
#define AT91C_SM_NCS_WR_PULSE	(3 << 8)		
#define AT91C_SM_NRD_PULSE		(2 << 16)		
#define AT91C_SM_NCS_RD_PULSE	(4 << 24)		
  
#define AT91C_SM_NWE_CYCLE 		(3 << 0)		
#define AT91C_SM_NRD_CYCLE		(5 << 16)		
  
#define AT91C_SM_TDF	        (1 << 16)		

#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC14;} while(0)
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC14;} while(0)

#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC15))

#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile unsigned char *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (unsigned char)(d); } while(0)
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile unsigned char *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (unsigned char)(d); } while(0)
#define WRITE_NAND(d, adr) do{ *(volatile unsigned char *)((unsigned long)adr) = (unsigned char)d; } while(0)
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile unsigned char *)(unsigned long)adr))

/* the following are NOP's in our implementation */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)

/* bits for nand_rw() `cmd'; or together as needed */
#define NANDRW_READ			0x01
#define NANDRW_WRITE		0x00
#define NANDRW_JFFS2		0x02
#define NANDRW_JFFS2_SKIP	0x04

/*------------------------------*/
/* External function Definition */
/*------------------------------*/

extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];

/* Current NAND Device	*/
extern int curr_device;

#endif /* NandFlash_h */