NULL, /* 0x14 */		NULL,		NULL,		NULL, /* 0x17 */		"Duron",		"K5",		"K6",		"K6-2",		"K6-3",		"Athlon",		"AMD2900",		"K6-2+",		"Power PC",		"Power PC 601",		"Power PC 603",		"Power PC 603+",		"Power PC 604",		"Power PC 620",		"Power PC x704",		"Power PC 750",		NULL, /* 0x28 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,/* 0x2F */		"Alpha",		"Alpha 21064",		"Alpha 21066",		"Alpha 21164",		"Alpha 21164PC",		"Alpha 21164a",		"Alpha 21264",		"Alpha 21364",		NULL, /* 0x38 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x3F */		"MIPS",		"MIPS R4000",		"MIPS R4200",		"MIPS R4400",		"MIPS R4600",		"MIPS R10000",		NULL, /* 0x46 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x4F */		"SPARC",		"SuperSPARC",		"MicroSPARC II",		"MicroSPARC IIep",		"UltraSPARC",		"UltraSPARC II",		"UltraSPARC IIi",		"UltraSPARC III",		"UltraSPARC IIIi",		NULL, /* 0x59 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x5F */		"68040",		"68xxx",		"68000",		"68010",		"68020",		"68030",		NULL, /* 0x66 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x6F */		"Hobbit",		NULL, /* 0x71 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x77 */		"Crusoe TM5000",		"Crusoe TM3000",		NULL, /* 0x7A */		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x7F */		"Weitek",		NULL, /* 0x81 */		"Itanium",		"Athlon 64",		"Opteron",		NULL, /* 0x85 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x8F */		"PA-RISC",		"PA-RISC 8500",		"PA-RISC 8000",		"PA-RISC 7300LC",		"PA-RISC 7200",		"PA-RISC 7100LC",		"PA-RISC 7100",		NULL, /* 0x97 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0x9F */		"V30",		NULL, /* 0xA1 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0xAF */		"Pentium III Xeon",		"Pentium III Speedstep",		"Pentium 4",		"Xeon",		"AS400",		"Xeon MP",		"Athlon XP",		"Athlon MP",		"Itanium 2",		NULL, /* 0xB9 */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0xC7 */		"IBM390",		"G4",		"G5",		NULL, /* 0xCB */		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL,		NULL, /* 0xF9 */		"i860",		"i960",		NULL, /* 0xFC */		NULL,		NULL,		NULL /* 0xFF */		/* master.mif has values beyond that, but they can't be used for DMI */	};		if(family[code]!=NULL)		return family[code];	return out_of_spec;}static void dmi_processor_id(u8 type, u8 *p, const char *version, const char *prefix){	/* Intel AP-485 revision 23, table 5 */	static const char *flags[32]={		"FPU (Floating-point unit on-chip)", /* 0 */		"VME (Virtual mode extension)",		"DE (Debugging extension)",		"PSE (Page size extension)",		"TSC (Time stamp counter)",		"MSR (Model specific registers)",		"PAE (Physical address extension)",		"MCE (Machine check exception)",		"CX8 (CMPXCHG8 instruction supported)",		"APIC (On-chip APIC hardware supported)",		NULL, /* 10 */		"SEP (Fast system call)",		"MTRR (Memory type range registers)",		"PGE (Page global enable)",		"MCA (Machine check architecture)",		"CMOV (Conditional move instruction supported)",		"PAT (Page attribute table)",		"PSE-36 (36-bit page size extension)",		"PSN (Processor serial number present and enabled)",		"CLFSH (CLFLUSH instruction supported)",		NULL, /* 20 */		"DS (Debug store)",		"ACPI (ACPI supported)",		"MMX (MMX technology supported)",		"FXSR (Fast floating-point save and restore)",		"SSE (Streaming SIMD extensions)",		"SSE2 (Streaming SIMD extensions 2)",		"SS (Self-snoop)",		"HTT (Hyper-threading technology)",		"TM (Thermal monitor supported)",		NULL, /* 30 */		"SBF (Signal break on FERR)" /* 31 */	};	/*	 * Extra flags are now returned in the ECX register when one calls	 * the CPUID instruction. Their means are explained in table 6, but	 * DMI doesn't support this yet.	 */	u32 eax;	int cpuid=0;	/*	 * This might help learn about new processors supporting the	 * CPUID instruction or another form of identification.	 */	printf("%sID: %02X %02X %02X %02X %02X %02X %02X %02X\n",		prefix, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);	if(type==0x05) /* 80386 */	{		u16 dx=WORD(p);		/*		 * 80386 have a different signature.		 */		printf("%sSignature: Type %X, Family %X, Major Stepping %X, Minor Stepping %X\n",			prefix, dx>>12, (dx>>8)&0xF, (dx>>4)&0xF, dx&0xF);		return;	}	if(type==0x06) /* 80486 */	{		u16 dx=WORD(p);		/*		 * Not all 80486 CPU support the CPUID instruction, we have to find		 * wether the one we have here does or not. Note that this trick		 * works only because we know that 80486 must be little-endian.		 */		if((dx&0x0F00)==0x0400 && ((dx&0x00F0)==0x0040 || (dx&0x00F0)>=0x0070))			cpuid=1;	}	else if((type>=0x0B && type<=0x13) /* Intel, Cyrix */	|| (type>=0x18 && type<=0x1D) || type==0x1F /* AMD */	|| (type>=0xB0 && type<=0xB3) /* Intel */	|| (type>=0xB5 && type<=0xB7)) /* Intel, AMD */		cpuid=1;	else if(type==0x01)	{		/*		 * Some X86-class CPU have family "Other". In this case, we use		 * the version string to determine if they are known to support the		 * CPUID instruction.		 */		if(strcmp(version, "AMD Athlon(TM) Processor")==0)			cpuid=1;		else			return;	}	else /* not X86-class */		return;		eax=DWORD(p);	printf("%sSignature: Type %X, Family %X, Model %X, Stepping %X\n",		prefix, (eax>>12)&0x3, ((eax>>16)&0xFF0)+((eax>>8)&0x00F),		((eax>>12)&0xF0)+((eax>>4)&0x0F), eax&0xF);	if(cpuid)	{		u32 edx=DWORD(p+4);				printf("%sFlags:", prefix);		if((edx&0x3FF7FDFF)==0)			printf(" None\n");		else		{			int i;						printf("\n");			for(i=0; i<=31; i++)				if(flags[i]!=NULL && edx&(1<<i))					printf("%s\t%s\n", prefix, flags[i]);		}	}}static void dmi_processor_voltage(u8 code){	/* 3.3.5.4 */	static const char *voltage[]={		"5.0 V", /* 0 */		"3.3 V",		"2.9 V" /* 2 */	};	int i;		if(code&0x80)		printf(" %.1f V", (float)(code&0x7f)/10);	else		for(i=0; i<=2; i++)			if(code&(1<<i))				printf(" %s", voltage[i]);}static void dmi_processor_frequency(u16 code){	if(code)		printf(" %u MHz", code);	else		printf(" Unknown");}static const char *dmi_processor_status(u8 code){	static const char *status[]={		"Unknown", /* 0x00 */		"Enabled",		"Disabled By User",		"Disabled By BIOS",		"Idle", /* 0x04 */		"Other" /* 0x07 */	};		if(code<=0x04)		return status[code];	if(code==0x07)		return status[0x05];	return out_of_spec;}static const char *dmi_processor_upgrade(u8 code){	/* 3.3.5.5 */	static const char *upgrade[]={		"Other", /* 0x01 */		"Unknown",		"Daughter Board",		"ZIF Socket",		"Replaceable Piggy Back",		"None",		"LIF Socket",		"Slot 1",		"Slot 2",		"370-pin Socket",		"Slot A",		"Slot M",		"Socket 423",		"Socket A (Socket 462)",		"Socket 478",		"Socket 754",		"Socket 940" /* 0x11 */	};		if(code>=0x01 && code<=0x11)		return upgrade[code-0x01];	return out_of_spec;}static void dmi_processor_cache(u16 code, const char *level, u16 ver){	if(code==0xFFFF)	{		if(ver>=0x0203)			printf(" Not Provided");		else			printf(" No %s Cache", level);	}	else		printf(" 0x%04X", code);}/* * 3.3.6 Memory Controller Information (Type 5) */static const char *dmi_memory_controller_ed_method(u8 code){	/* 3.3.6.1 */	static const char *method[]={		"Other", /* 0x01 */		"Unknown",		"None",		"8-bit Parity",		"32-bit ECC",		"64-bit ECC",		"128-bit ECC",		"CRC" /* 0x08 */	};		if(code>=0x01 && code<=0x08)		return(method[code-0x01]);	return out_of_spec;}static void dmi_memory_controller_ec_capabilities(u8 code, const char *prefix){	/* 3.3.6.2 */	static const char *capabilities[]={		"Other", /* 0 */		"Unknown",		"None",		"Single-bit Error Correcting",		"Double-bit Error Correcting",		"Error Scrubbing" /* 5 */	};		if((code&0x3F)==0)		printf(" None\n");	else	{		int i;				printf("\n");		for(i=0; i<=5; i++)			if(code&(1<<i))				printf("%s%s\n", prefix, capabilities[i]);	}}static const char* dmi_memory_controller_interleave(u8 code){	/* 3.3.6.3 */	static const char *interleave[]={		"Other", /* 0x01 */		"Unknown",		"One-way Interleave",		"Two-way Interleave",		"Four-way Interleave",		"Eight-way Interleave",		"Sixteen-way Interleave" /* 0x07 */	};		if(code>=0x01 && code<=0x07)		return(interleave[code-0x01]);	return(out_of_spec);}static void dmi_memory_controller_speeds(u16 code, const char *prefix){	/* 3.3.6.4 */	const char *speeds[]={		"Other", /* 0 */		"Unknown",		"70 ns",		"60 ns",		"50 ns" /* 4 */	};		if((code&0x001F)==0)		printf(" None\n");	else	{		int i;				printf("\n");		for(i=0; i<=4; i++)			if(code&(1<<i))				printf("%s%s\n", prefix, speeds[i]);	}}static void dmi_memory_controller_slots(u8 count, u8 *p, const char *prefix){	int i;		printf("%sAssociated Memory Slots: %u\n",		prefix, count);	for(i=0; i<count; i++)		printf("%s\t0x%04X\n",			prefix, WORD(p+sizeof(u16)*i));}/* * 3.3.7 Memory Module Information (Type 6) */static void dmi_memory_module_types(u16 code, const char *sep){	/* 3.3.7.1 */	static const char *types[]={		"Other", /* 0 */		"Unknown",		"Standard",		"FPM",		"EDO",		"Parity",		"ECC",		"SIMM",		"DIMM",		"Burst EDO",		"SDRAM" /* 10 */	};		if((code&0x03FF)==0)		printf(" None");	else	{		int i;				for(i=0; i<=10; i++)			if(code&(1<<i))				printf("%s%s", sep, types[i]);	}}static void dmi_memory_module_connections(u8 code){	if(code==0xFF)		printf(" None");	else	{		if((code&0xF0)!=0xF0)			printf(" %u", code>>4);		if((code&0x0F)!=0x0F)			printf(" %u", code&0x0F);	}}static void dmi_memory_module_speed(u8 code){	if(code==0)		printf(" Unknown");	else		printf(" %u ns", code);}static void dmi_memory_module_size(u8 code){	/* 3.3.7.2 */	switch(code&0x7F)	{		case 0x7D:			printf(" Not Determinable");			break;		case 0x7E:			printf(" Disabled");			break;		case 0x7F:			printf(" Not Installed");			break;		default:			printf(" %u MB", 1<<(code&0x7F));	}		if(code&0x80)		printf(" (Double-bank Connection)");	else		printf(" (Single-bank Connection)");}static void dmi_memory_module_error(u8 code, const char *prefix){	if(code&(1<<2))		printf(" See Event Log\n");	else	{	if((code&0x03)==0)			printf(" OK\n");		if(code&(1<<0))			printf("%sUncorrectable Errors\n", prefix);		if(code&(1<<1))			printf("%sCorrectable Errors\n", prefix);	}}