Model {
  Name			  "c4falg1c"
  Version		  4.00
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowStorageClass	  off
  ExecutionOrder	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Tue Sep 04 08:38:28 2001"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Sun Sep 23 02:25:26 2001"
  ModelVersionFormat	  "1.%<AutoIncrement:3>"
  ConfigurationManager	  "none"
  SimParamPage		  "Solver"
  StartTime		  "0.0"
  StopTime		  "10.0"
  SolverMode		  "Auto"
  Solver		  "ode45"
  RelTol		  "1e-3"
  AbsTol		  "auto"
  Refine		  "1"
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  MaxOrder		  5
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  SaveTime		  on
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  on
  OutputSaveName	  "yout"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  LimitDataPoints	  on
  MaxDataPoints		  "1000"
  Decimation		  "1"
  AlgebraicLoopMsg	  "warning"
  MinStepSizeMsg	  "warning"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  SingleTaskRateTransMsg  "none"
  MultiTaskRateTransMsg	  "error"
  IntegerOverflowMsg	  "warning"
  CheckForMatrixSingularity "none"
  UnnecessaryDatatypeConvMsg "none"
  Int32ToFloatConvMsg	  "warning"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  LinearizationMsg	  "none"
  VectorMatrixConversionMsg "none"
  SfunCompatibilityCheckMsg "none"
  BlockPriorityViolationMsg "warning"
  ArrayBoundsChecking	  "none"
  ConsistencyChecking	  "none"
  ZeroCross		  on
  Profile		  off
  SimulationMode	  "normal"
  RTWSystemTargetFile	  "grt.tlc"
  RTWInlineParameters	  off
  RTWRetainRTWFile	  off
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  OptimizeBlockIOStorage  on
  BufferReuse		  on
  ParameterPooling	  on
  BlockReductionOpt	  off
  RTWExpressionDepthLimit 5
  BooleanDataType	  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "c4falg1c"
    Location		    [482, 83, 982, 384]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "automatic"
    PaperOrientation	    "portrait"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "LTI System"
      Ports		      [1, 1]
      Position		      [145, 137, 240, 173]
      SourceBlock	      "cstblocks/LTI System"
      SourceType	      "LTI Block"
      sys		      "Gc"
      IC		      "[]"
    }
    Block {
      BlockType		      Step
      Name		      "Step"
      Position		      [35, 115, 65, 145]
      Time		      "0"
      Before		      "0"
      After		      "1"
      SampleTime	      "0"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Outport
      Name		      "Out1"
      Position		      [305, 148, 335, 162]
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Line {
      SrcBlock		      "Step"
      SrcPort		      1
      Points		      [60, 0]
      DstBlock		      "LTI System"
      DstPort		      1
    }
    Line {
      SrcBlock		      "LTI System"
      SrcPort		      1
      DstBlock		      "Out1"
      DstPort		      1
    }
    Annotation {
      Position		      [75, 177]
      Text		      "c4falg1c.mdl"
      FontName		      "Arial"
      FontSize		      12
      FontWeight	      "bold"
    }
  }
}