#define UART_IER_LINESTSINT  0x00000004#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */#define UART_IER_XOFFINT     0x00000020#define UART_IER_RTSINT      0x00000040 /* IrDA UART only */#define UART_IER_CTSINT      0x00000080 /* IrDA UART only */#define UART_IER_INTMASK     0x000000ff#define BAUD_115200          0x00000001#define BAUD_57600           0x00000002#define BAUD_38400           0x00000003#define BAUD_19200           0x00000006#define BAUD_9600            0x0000000C#define BAUD_4800            0x00000018#define BAUD_2400            0x00000030#define BAUD_1200            0x00000060#define MDR_UART_MODE        0x00000000  /* Both IrDA and Modem UARTs */#define MDR_SIR_MODE         0x00000001  /* IrDA UART only */#define MDR_AUTOBAUDING_MODE 0x00000002  /* Modem UART only */#define MDR_RESET_MODE       0x00000007  /* Both IrDA and Modem UARTs *//* SPI **********************************************************************/#define MAX_SPI 3#define SPI_REGISTER_BASE    0xffff2000/* GIO **********************************************************************/#define MAX_GIO (35)#define GIO_REGISTER_BASE    0xffff2800#define GPIO_IO              0xffff2800 /* Writeable when I/O is configured					 * as an output; reads value on I/O					 * pin when I/O is configured as an					 * input */#define GPIO_CIO             0xffff2804 /* GPIO configuration register */#define GPIO_IRQA            0xffff2808 /* In conjunction with GPIO_IRQB					 * determines the behavior when GPIO					 * pins configured as input IRQ */#define GPIO_IRQB            0xffff280c /* Determines the behavior when GPIO					 * pins configured as input IRQ */#define GPIO_DDIO            0xffff2810 /* Delta Detect Register					 * (detects changes in the I/O pins) */#define GPIO_EN              0xffff2814 /* Selects register for muxed GPIOs */#define KGIO_REGISTER_BASE   0xffff2900#define KBGPIO_IO            0xffff2900 /* Keyboard I/O bits: Writeable					 * when KBGPIO is configured as an					 * output; reads value on I/O pin					 * when KBGPIO is configured as an					 * input */#define KBGPIO_CIO           0xffff2904 /* KBGPIO configuration register */#define KBGPIO_IRQA          0xffff2908 /* In conjunction with KBGPIO_IRQB					 * determines the behavior when					 * KBGPIO pins configured as input					 * IRQ */#define KBGPIO_IRQB          0xffff290c /* In conjunction with KBGPIO_IRQA					 * determines the behavior when					 * KBGPIO pins configured as input					 * IRQ */#define KBGPIO_DDIO          0xffff2910 /* Delta Detect Register (detects					 * changes in the KBGPIO pins) */#define KBGPIO_EN            0xffff2914 /* Selects register for muxed					 * KBGPIOs *//* Timers *******************************************************************/#define C5471_TIMER0_CTRL    0xffff2a00#define C5471_TIMER0_CNT     0xffff2a04#define C5471_TIMER1_CTRL    0xffff2b00#define C5471_TIMER1_CNT     0xffff2b04#define C5471_TIMER2_CTRL    0xffff2c00#define C5471_TIMER2_CNT     0xffff2c04/* Interrupts */#define HAVE_SRC_IRQ_BIN_REG 0#define INT_FIRST_IO         0xffff2d00#define INT_IO_RANGE         0x5C#define IT_REG               0xffff2d00#define MASK_IT_REG          0xffff2d04#define SRC_IRQ_REG          0xffff2d08#define SRC_FIQ_REG          0xffff2d0c#define SRC_IRQ_BIN_REG      0xffff2d10#define INT_CTRL_REG         0xffff2d18#define ILR_IRQ0_REG         0xffff2d1C /*  0-Timer 0       */#define ILR_IRQ1_REG         0xffff2d20 /*  1-Timer 1       */#define ILR_IRQ2_REG         0xffff2d24 /*  2-Timer 2       */#define ILR_IRQ3_REG         0xffff2d28 /*  3-GPIO0         */#define ILR_IRQ4_REG         0xffff2d2c /*  4-Ethernet      */#define ILR_IRQ5_REG         0xffff2d30 /*  5-KBGPIO[7:0]   */#define ILR_IRQ6_REG         0xffff2d34 /*  6-Uart serial   */#define ILR_IRQ7_REG         0xffff2d38 /*  7-Uart IRDA     */#define ILR_IRQ8_REG         0xffff2d3c /*  8-KBGPIO[15:8]  */#define ILR_IRQ9_REG         0xffff2d40 /*  9-GPIO3         */#define ILR_IRQ10_REG        0xffff2d44 /* 10-GPIO2         */#define ILR_IRQ11_REG        0xffff2d48 /* 11-I2C           */#define ILR_IRQ12_REG        0xffff2d4c /* 12-GPIO1         */#define ILR_IRQ13_REG        0xffff2d50 /* 13-SPI           */#define ILR_IRQ14_REG        0xffff2d54 /* 14-GPIO[19:4]    */#define ILR_IRQ15_REG        0xffff2d58 /* 15-API           *//* CLKM *********************************************************************/#define CLKM                 0xffff2f00#define CLKM_CTL_RST         0xffff2f10#define CLKM_RESET           0xffff2f18#define CLKM_RESET_EIM          0x00000008#define CLKM_EIM_CLK_STOP       0x00000010#define CLKM_CTL_RST_LEAD_RESET 0x00000000#define CLKM_CTL_RST_EXT_RESET  0x00000002/* I2C **********************************************************************/#define MAX_I2C 1/* API **********************************************************************/#define DSPRAM_BASE          0xffe00000  /* DSPRAM base address */#define DSPRAM_END           0xffe03fff/* This is the API address range in the DSP address space. */#define DSPMEM_DSP_START     0x2000#define DSPMEM_DSP_END       0x3fff/* This is the API address range in the ARM address space. */#define DSPMEM_ARM_START     DSPRAM_BASE /* Defined in hardware.h */#define DSPMEM_ARM_END       DSPRAM_END/* DSPMEM_IN_RANGE is a generic macro to test is a value is within * a range of values. */#define DSPMEM_IN_RANGE(addr, start, end) \  ((((__u32)(addr)) >= (start)) && (((__u32)(addr)) <= (end)))/* DSPMEM_ADDR_ALIGNED verifies that a potential DSP address is * properly word aligned. */#define DSPMEM_ADDR_ALIGNED(addr, cpu) ((((__u32)(addr)) & 1) == 0)/* DSPMEM_DSP_ADDR checks if a DSP address lies in within the * DSP's API address range. */#define DSPMEM_DSP_ADDR(addr, cpu) \  DSPMEM_IN_RANGE(addr, DSPMEM_DSP_START, DSPMEM_DSP_END)/* DSPMEM_ARM_ADDR checks if a ARM address lies in within the * ARM's API address range. */#define DSPMEM_ARM_ADDR(addr) \  DSPMEM_IN_RANGE(addr, DSPMEM_ARM_START, DSPMEM_ARM_END)/* DSPMEM_DSP_TO_ARM maps a DSP API address into an ARM API address */#define DSPMEM_DSP_TO_ARM(addr, cpu) \  ((((__u32)(addr) - DSPMEM_DSP_START) << 1) + DSPMEM_ARM_START)/* DSPMEM_ARM_TO_DSP maps an ARM API address into a DSP API address */#define DSPMEM_ARM_TO_DSP(addr) \  ((((__u32)(addr) - DSPMEM_ARM_START) >> 1) + DSPMEM_DSP_START)/**************************************************************************** * Inline Functions ****************************************************************************//**************************************************************************** * Public Function Prototypes ****************************************************************************/#endif  /* __C5471_CHIP_H */