?? camera.c
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/**************************************************************************************
*
* Project Name : S3C6400 Validation
*
* Copyright 2006 by Samsung Electronics, Inc.
* All rights reserved.
*
* Project Description :
* This software is only for validating functions of the S3C6400.
* Anybody can use this software without our permission.
*
*--------------------------------------------------------------------------------------
*
* File Name : camera.c
*
* File Description : Camera API Function
*
* Author :
* Dept. : AP Development Team
* Created Date :
* Version : 0.1
*
* History
* - Created
*
**************************************************************************************/
#include <string.h>
#include <stdio.h>
#include "def.h"
#include "system.h"
#include "lcd.h"
#include "camera.h"
#include "cameram.h"
//#include "CameraModule.h"
#include "glib.h"
#include "intc.h"
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "sysc.h"
#include "gpio.h"
#define CAMERAR ( ( volatile oCAMERA_REGS * ) CAMERA_pBase )
static void *CAMERA_pBase;
typedef struct tag_CAMERA_REGS
{
u32 rCISRCFMT; // 0x7800_0000 Camera Input Sorce Format
u32 rCIWDOFST; // 0x7800_0004 Window Offset Register
u32 rCIGCTRL; // 0x7800_0008 Golbal Control Register
u32 rreserved0;
u32 rreserved1;
u32 rCIDOWFST2; // 0x7800_0014 Window Offset Register 2
u32 rCICOYSA1; // 0x7800_0018 Interleace YCbCr, Non Interleave Y, RGB : 1st Frame Start Address for Codec DMA
u32 rCICOYSA2; // 0x7800_001C Interleace YCbCr, Non Interleave Y, RGB : 2st Frame Start Address for Codec DMA
u32 rCICOYSA3; // 0x7800_0020 Interleace YCbCr, Non Interleave Y, RGB : 3st Frame Start Address for Codec DMA
u32 rCICOYSA4; // 0x7800_0024 Interleace YCbCr, Non Interleave Y, RGB : 4st Frame Start Address for Codec DMA
u32 rCICOCBSA1; // 0x7800_0028 Cb 1st Frame Start Address for Codec DMA
u32 rCICOCBSA2; // 0x7800_002C Cb 2st Frame Start Address for Codec DMA
u32 rCICOCBSA3; // 0x7800_0030 Cb 3st Frame Start Address for Codec DMA
u32 rCICOCBSA4; // 0x7800_0034 Cb 4st Frame Start Address for Codec DMA
u32 rCICOCRSA1; // 0x7800_0038 Cr 1st Frame Start Address for Codec DMA
u32 rCICOCRSA2; // 0x7800_003C Cr 2st Frame Start Address for Codec DMA
u32 rCICOCRSA3; // 0x7800_0040 Cr 3st Frame Start Address for Codec DMA
u32 rCICOCRSA4; // 0x7800_0044 Cr 4st Frame Start Address for Codec DMA
u32 rCICOTRGFMT; // 0x7800_0048 Targer Image Format of Codec DMA
u32 rCICOCTRL; // 0x7800_004C Codec DMA Control Related
u32 rCICOSCPRERATIO; // 0x7800_0050 Codec Pre_Scaler Ratio Control
u32 rCICOSCPREDST; // 0x7800_0054 Codec Pre_Scaler Destination Format
u32 rCICOSCCTRL; // 0x7800_0058 Codec Main_Scaler Control
u32 rCICOTAREA; // 0x7800_005C Codec Pre_Scaler Destination Format(Area)
u32 rreserved3;
u32 rCICOSTATUS; // 0x7800_0064 Codec Path Status
u32 rreserved4;
u32 rCIPRYSA1; // 0x7800_006C Interleace YCbCr, Non Interleave Y, RGB : 1st Frame Start Address for Preview DMA
u32 rCIPRYSA2; // 0x7800_0070 Interleace YCbCr, Non Interleave Y, RGB : 2st Frame Start Address for Preview DMA
u32 rCIPRYSA3; // 0x7800_0074 Interleace YCbCr, Non Interleave Y, RGB : 3st Frame Start Address for Preview DMA
u32 rCIPRYSA4; // 0x7800_0078 Interleace YCbCr, Non Interleave Y, RGB : 4st Frame Start Address for Preview DMA
u32 rCIPRCBSA1; // 0x7800_007C Cb, 1st Frame Start Address for Preview DMA
u32 rCIPRCBSA2; // 0x7800_0080 Cb, 2st Frame Start Address for Preview DMA
u32 rCIPRCBSA3; // 0x7800_0084 Cb, 3st Frame Start Address for Preview DMA
u32 rCIPRCBSA4; // 0x7800_0088 Cb, 4st Frame Start Address for Preview DMA
u32 rCIPRCRSA1; // 0x7800_008C Cr, 1st Frame Start Address for Preview DMA
u32 rCIPRCRSA2; // 0x7800_0090 Cr, 2st Frame Start Address for Preview DMA
u32 rCIPRCRSA3; // 0x7800_0094 Cr, 3st Frame Start Address for Preview DMA
u32 rCIPRCRSA4; // 0x7800_0098 Cr, 4st Frame Start Address for Preview DMA
u32 rCIPRTRGFMT; // 0x7800_009C Target Image For Preview DMA
u32 rCIPRCTRL; // 0x7800_00A0 Preview DMA Control Releated
u32 rCIPRSCPRERATIO; // 0x7800_00A4 Preview Pre_Scaler Ratio Control
u32 rCIPRSCPREDST; // 0x7800_00A8 Preview Pre_Scaler Destination Format
u32 rCIPRSCCTRL; // 0x7800_00AC Preview Main Scaler Control
u32 rCIPRTAREA; // 0x7800_00B0 Preview Pre_Scaler Destination Format(Area)
u32 rreserved5;
u32 rCIPRSTATUS; // 0x7800_00B8 Preview Path Status
u32 rreserved6;
u32 rCIIMGCPT; // 0x7800_00C0 Image Capture Enable Command
u32 rCICPTSEQ; // 0x7800_00C4 Camera Image Capture Sequence Related
u32 rreserved7;
u32 rreserved8;
u32 rCIIMGEFF; // 0x7800_00D0 Image Effects Related
u32 rMSCOY0SA; // 0x7800_00D4 MSDMA Y0 Start Address Related
u32 rMSCOCB0SA; // 0x7800_00D8 MSDMA Cb0 Start Address Related
u32 rMSCOCR0SA; // 0x7800_00DC MSDMA Cr0 Start Address Related
u32 rMSCOY0END; // 0x7800_00E0 MSDMA Y0 End Address Related
u32 rMSCOCB0END; // 0x7800_00E4 MSDMA Cb0 End Address Related
u32 rMSCOCR0END; // 0x7800_00E8 MSDMA Cr0 End Address Related
u32 rMSCOYOFF; // 0x7800_00EC MSDMA Y Offset Related
u32 rMSCOCBOFF; // 0x7800_00F0 MSDMA Cb Offset Related
u32 rMSCOCROFF; // 0x7800_00F4 MSDMA Cr Offset Related
u32 rMSCOWIDTH; // 0x7800_00F8 MSDMA Source Image Width Related
u32 rMSCOCTRL; // 0x7800_00FC MSDMA for Codec Control Register
u32 rMSPRY0SA; // 0x7800_0100 MSDMA Y0 Start Address Related(Preview)
u32 rMSPRCB0SA; // 0x7800_0104 MSDMA Cb0 Start Address Related(Preview)
u32 rMSPRCR0SA; // 0x7800_0108 MSDMA Cr0 Start Address Related(Preview)
u32 rMSPRY0END; // 0x7800_010C MSDMA Y0 End Address Related(Preview)
u32 rMSPRCB0END; // 0x7800_0110 MSDMA Cb0 End Address Related(Preview)
u32 rMSPRCR0END; // 0x7800_0114 MSDMA Cr0 End Address Related(Preview)
u32 rMSPRYOFF; // 0x7800_0118 MSDMA Y Offset Related(Preview)
u32 rMSPRCBOFF; // 0x7800_011C MSDMA Cb Offset Related(Preview)
u32 rMSPRCROFF; // 0x7800_0120 MSDMA Cr Offset Related(Preview)
u32 rMSPRWIDTH; // 0x7800_0124 MSDMA Source Image Width RElated(Preview)
u32 rCIMSCTRL; // 0x7800_0128 MSDMA Control Register for Preview
u32 rCICOSCOSY; // 0x7800_012C Codec Scan Line Y Offset Related
u32 rCICOSCOSCB; // 0x7800_0130 Codec Scan Line Cb Offset Related
u32 rCICOSCOSCR; // 0x7800_0134 Codec Scan Line Cr Offset Related
u32 rCIPRSCOSY; // 0x7800_0138 Preview Scan Line Y Offset Related
u32 rCIPRSCOSCB; // 0x7800_013C Preview Scan Line Cb Offset Related
u32 rCIPRSCOSCR; // 0x7800_0140 Preview Scna Line Cr Offset Related
}oCAMERA_REGS;
CIM oCim;
static volatile u32 CAMTYPE;
#define SCALER_BYPASS_MAX_HSIZE 4096
#define SCALER_MAX_HSIZE_P 640
#define SCALER_MAX_HSIZE_C 1600
#define OUTPUT_MAX_HSIZE_ROT_RGB_P 320
#define OUTPUT_MAX_HSIZE_ROT_RGB_C 800
#define INPUT_MAX_HSIZE_ROT_P 160
#define INPUT_MAX_VSIZE_ROT_P 120
#define INPUT_MAX_HSIZE_ROT_C 720
#define INPUT_MAX_VSIZE_ROT_C 576
/*
//////////
// Function Name : CAMERA_ReadCameraModuleStatus
// Function Description : Camerar Module 1.3M(SXGA) 2M(UXGA) IIC Initial Setting Value Write / Read
// Input :
// Output : None
void CAMERA_ReadCameraModuleStatus(void)
{
#if (CAM_MODEL == CAM_S5K3AA)
oCim.m_eCcir = CCIR656;
oCim.m_eCamSrcFmt = CBYCRY;
CAMTYPE = 0;
CAMERA_Read_Write(CAMTYPE,oCim.m_eCcir, oCim.m_eCamSrcFmt, VGA);
#elif (CAM_MODEL == CAM_S5K3BA) ///
oCim.m_eCcir = CCIR601;
oCim.m_eCamSrcFmt = YCRYCB;
CAMTYPE = 1;
CAMERA_Read_Write(CAMTYPE,oCim.m_eCcir, oCim.m_eCamSrcFmt, SUB_SAMPLING0);
#else
Assert(0);
#endif
}
*/
//////////
// Function Name : CAMERA_ClkSetting
// Function Description : Camera CLK output setting. using HCLKx2
// Input : None
// Output : None
void CAMERA_ClkSetting(void)
{
u32 uCamCLKDiver;
u32 uHCLKx2;
SYSC_GetClkInform();
printf("\n----------------------------------------------------------------------------------------\n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
uHCLKx2 = (int)(g_HCLKx2/1000000);
switch ( uHCLKx2)
{
case 200:
printf (" CAMCLK Source is HCLKx2 = 200 Mhz \n");
printf (" CAMCLK = 200 / (1+7) = 25Mhz Setting \n");
uCamCLKDiver = Inp32SYSC(0x20);
uCamCLKDiver = ( uCamCLKDiver & ~(0xf<<20)) | (7<<20); // 200 Mhz / (9+1) = 25Mhz...
// uCamCLKDiver = ( uCamCLKDiver & ~(0xf<<20)) | (12<<20); // 200 Mhz / (9+1) = 20Mhz...
Outp32SYSC(0x20, uCamCLKDiver);
break;
case 266:
printf (" CAMCLK Source is HCLKx2 = 266 Mhz =");
printf (" CAMCLK = 266 / (1+9) = 26Mhz Setting =");
uCamCLKDiver = Inp32SYSC(0x20);
uCamCLKDiver = ( uCamCLKDiver & ~(0xf<<20)) | (9<<20); // 266 Mhz / (9+1) = 26Mhz...
Outp32SYSC(0x20, uCamCLKDiver);
break;
default:
printf("Check HCLKx2 is 200 or 266Mhz!!\n");
Assert(0);
break;
}
#if 0
// CamCLK Source is HCLK
printf("\n===============================");
printf ("\n= CAMCLK Source is HCLKx2 = 200 Mhz =");
printf ("\n= CAMCLK = 200 / (1+9) = 20Mhz Setting =");
printf("\n===============================");
uCamCLKDiver = Inp32SYSC(0x20);
uCamCLKDiver = ( uCamCLKDiver & ~(0xf<<20)) | (9<<20); // 200 Mhz / (9+1) = 20Mhz...
Outp32SYSC(0x20, uCamCLKDiver);
#endif
}
//////////
// Function Name : CAMERA_InitSensor
// Function Description : Camera Moudle Init
// Input : None
// Output : None
void CAMERA_InitSensor(void)
{
// 1. Reset sensor
//==========================================
CAMERA_ResetSensor();
Delay(5000);
// 2. Initalize the member variables and initalize the camera model.
//==========================================
oCim.m_uIfBits = 8;
#if (CAM_MODEL == CAM_S5K3AA)
oCim.m_bInvPclk = true,
oCim.m_bInvVsync = false,
oCim.m_bInvHref = false;
oCim.m_uSrcHsz = 640, oCim.m_uSrcVsz = 480;
// oCim.m_uSrcHsz = 1280, oCim.m_uSrcVsz = 1024;
oCim.m_eCcir = CCIR656;
oCim.m_eCamSrcFmt = CBYCRY;
// oCim.m_eCamSrcFmt = YCRYCB;
CAMTYPE = 0;
CAMERA_InitS5K3AAE_VGA();
#elif (CAM_MODEL == CAM_S5K3BA) ///
oCim.m_bInvPclk = false,
oCim.m_bInvVsync = true,
oCim.m_bInvHref = false;
oCim.m_uSrcHsz = 800, oCim.m_uSrcVsz = 600;
// oCim.m_uSrcHsz = 1280, oCim.m_uSrcVsz = 1024;
oCim.m_eCcir = CCIR601;
oCim.m_eCamSrcFmt = YCRYCB;
CAMTYPE = 1;
CAMERA_InitS5K3BAF(oCim.m_eCcir, oCim.m_eCamSrcFmt, SUB_SAMPLING2);
#elif (CAM_MODEL == CAM_A3AFX_VGA) ///
oCim.m_bInvPclk = false,
oCim.m_bInvVsync = true,
oCim.m_bInvHref = false;
oCim.m_uSrcHsz = 320, oCim.m_uSrcVsz = 240;
// oCim.m_uSrcHsz = 176, oCim.m_uSrcVsz = 144;
oCim.m_eCcir = CCIR601;
oCim.m_eCamSrcFmt = YCBYCR;
CAMERA_InitA3AFX_QVGA_20FR();
// CAMERA_InitA3AFX_QVGA_15FR();
// CAMERA_InitA3AFX_QCIF_30FR();
// CAMERA_InitA3AFX_QCIF_15FR();
#else
Assert(0);
#endif
}
//////////
// Function Name : CAMERA_InitSensor1
// Function Description : This Function use at JPEG Test.
// Input : IMG_SIZE eSize(Image Size), CAM_ATTR eCcir(Source YCBCR Format), CSPACE eSrcFmt(Source Format)
// Output : None
void CAMERA_InitSensor1(IMG_SIZE eSize, CAM_ATTR eCcir, CSPACE eSrcFmt)
{
SUB_SAMPLING eSub;
// 1. Reset sensor
//==========================================
CAMERA_ResetSensor();
// 2. Initalize the member variables and initalize the camera model.
//==========================================
oCim.m_uIfBits = 8;
oCim.m_eCcir = eCcir;
oCim.m_eCamSrcFmt = eSrcFmt;
if (eSize == UXGA)
oCim.m_uSrcHsz = 1600, oCim.m_uSrcVsz = 1200;
else if (eSize == SXGA)
oCim.m_uSrcHsz = 1280, oCim.m_uSrcVsz = 1024;
else if (eSize == SVGA)
oCim.m_uSrcHsz = 800, oCim.m_uSrcVsz = 600;
else if (eSize == VGA)
oCim.m_uSrcHsz = 640, oCim.m_uSrcVsz = 480;
else if (eSize == QVGA)
oCim.m_uSrcHsz = 320, oCim.m_uSrcVsz = 240;
else if (eSize == QQVGA)
oCim.m_uSrcHsz = 160, oCim.m_uSrcVsz = 120;
else if (eSize == CIF)
oCim.m_uSrcHsz = 352, oCim.m_uSrcVsz = 288;
else if (eSize == QCIF)
oCim.m_uSrcHsz = 172, oCim.m_uSrcVsz = 144;
else
{
Assert(0);
}
#if (CAM_MODEL == CAM_S5K3AA)
Assert( oCim.m_eCcir == CCIR656);
oCim.m_bInvPclk = true,
oCim.m_bInvVsync = false,
oCim.m_bInvHref = false;
oCim.m_eCamSrcFmt = CBYCRY;
CAMERA_InitS5K3AAE(oCim.m_eCcir, oCim.m_eCamSrcFmt, SXGA);
#elif (CAM_MODEL == CAM_S5K4AAF)
oCim.m_bInvPclk = false,
oCim.m_bInvVsync = false,
oCim.m_bInvHref = false;
oCim.m_eCamSrcFmt = YCRYCB; // change camif setting instead of cam module.
oCim.m_oCamera.InitS5K4AAF(oCim.m_eCcir, oCim.m_eCamSrcFmt, eSize);
#elif (CAM_MODEL == CAM_S5K3BA)
Assert( oCim.m_eCcir == CCIR601);
oCim.m_bInvPclk = false,
oCim.m_bInvVsync = true,
oCim.m_bInvHref = false;
oCim.m_eCamSrcFmt = YCRYCB;
switch(eSize)
{
case UXGA:case SXGA:
eSub = SUB_SAMPLING0;
oCim.m_uSrcHsz = 1600; oCim.m_uSrcVsz = 1200;
break;
case SVGA:case VGA:
eSub = SUB_SAMPLING2;
oCim.m_uSrcHsz = 800; oCim.m_uSrcVsz = 600;
break;
case QVGA:case QQVGA:case CIF:case QCIF:
eSub = SUB_SAMPLING4;
oCim.m_uSrcHsz = 400; oCim.m_uSrcVsz = 300;
break;
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