int	       *list;} drm_buf_free_t;typedef struct drm_buf_pub {	int		  idx;	       /* Index into master buflist	     */	int		  total;       /* Buffer size			     */	int		  used;	       /* Amount of buffer in use (for DMA)  */	void		  *address;    /* Address of buffer		     */} drm_buf_pub_t;typedef struct drm_buf_map {	int	      count;	/* Length of buflist			    */	void	      *virtual;	/* Mmaped area in user-virtual		    */	drm_buf_pub_t *list;	/* Buffer information			    */} drm_buf_map_t;typedef struct drm_dma {				/* Indices here refer to the offset into				   buflist in drm_buf_get_t.  */	int		context;	  /* Context handle		    */	int		send_count;	  /* Number of buffers to send	    */	int		*send_indices;	  /* List of handles to buffers	    */	int		*send_sizes;	  /* Lengths of data to send	    */	drm_dma_flags_t flags;		  /* Flags			    */	int		request_count;	  /* Number of buffers requested    */	int		request_size;	  /* Desired size for buffers	    */	int		*request_indices; /* Buffer information		    */	int		*request_sizes;	int		granted_count;	  /* Number of buffers granted	    */} drm_dma_t;typedef enum {	_DRM_CONTEXT_PRESERVED = 0x01,	_DRM_CONTEXT_2DONLY    = 0x02} drm_ctx_flags_t;typedef struct drm_ctx {	drm_context_t	handle;	drm_ctx_flags_t flags;} drm_ctx_t;typedef struct drm_ctx_res {	int		count;	drm_ctx_t	*contexts;} drm_ctx_res_t;typedef struct drm_draw {	drm_drawable_t	handle;} drm_draw_t;typedef struct drm_auth {	drm_magic_t	magic;} drm_auth_t;typedef struct drm_irq_busid {	int irq;	int busnum;	int devnum;	int funcnum;} drm_irq_busid_t;typedef struct drm_agp_mode {	unsigned long mode;} drm_agp_mode_t;				/* For drm_agp_alloc -- allocated a buffer */typedef struct drm_agp_buffer {	unsigned long size;	/* In bytes -- will round to page boundary */	unsigned long handle;	/* Used for BIND/UNBIND ioctls */	unsigned long type;     /* Type of memory to allocate  */        unsigned long physical; /* Physical used by i810       */} drm_agp_buffer_t;				/* For drm_agp_bind */typedef struct drm_agp_binding {	unsigned long handle;   /* From drm_agp_buffer */	unsigned long offset;	/* In bytes -- will round to page boundary */} drm_agp_binding_t;typedef struct drm_agp_info {	int            agp_version_major;	int            agp_version_minor;	unsigned long  mode;	unsigned long  aperture_base;  /* physical address */	unsigned long  aperture_size;  /* bytes */	unsigned long  memory_allowed; /* bytes */	unsigned long  memory_used;				/* PCI information */	unsigned short id_vendor;	unsigned short id_device;} drm_agp_info_t;#define DRM_IOCTL_BASE			'd'#define DRM_IO(nr)			_IO(DRM_IOCTL_BASE,nr)#define DRM_IOR(nr,size)		_IOR(DRM_IOCTL_BASE,nr,size)#define DRM_IOW(nr,size)		_IOW(DRM_IOCTL_BASE,nr,size)#define DRM_IOWR(nr,size)		_IOWR(DRM_IOCTL_BASE,nr,size)#define DRM_IOCTL_VERSION		DRM_IOWR(0x00, drm_version_t)#define DRM_IOCTL_GET_UNIQUE		DRM_IOWR(0x01, drm_unique_t)#define DRM_IOCTL_GET_MAGIC		DRM_IOR( 0x02, drm_auth_t)#define DRM_IOCTL_IRQ_BUSID		DRM_IOWR(0x03, drm_irq_busid_t)#define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, drm_unique_t)#define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, drm_auth_t)#define DRM_IOCTL_BLOCK			DRM_IOWR(0x12, drm_block_t)#define DRM_IOCTL_UNBLOCK		DRM_IOWR(0x13, drm_block_t)#define DRM_IOCTL_CONTROL		DRM_IOW( 0x14, drm_control_t)#define DRM_IOCTL_ADD_MAP		DRM_IOWR(0x15, drm_map_t)#define DRM_IOCTL_ADD_BUFS		DRM_IOWR(0x16, drm_buf_desc_t)#define DRM_IOCTL_MARK_BUFS		DRM_IOW( 0x17, drm_buf_desc_t)#define DRM_IOCTL_INFO_BUFS		DRM_IOWR(0x18, drm_buf_info_t)#define DRM_IOCTL_MAP_BUFS		DRM_IOWR(0x19, drm_buf_map_t)#define DRM_IOCTL_FREE_BUFS		DRM_IOW( 0x1a, drm_buf_free_t)#define DRM_IOCTL_ADD_CTX		DRM_IOWR(0x20, drm_ctx_t)#define DRM_IOCTL_RM_CTX		DRM_IOWR(0x21, drm_ctx_t)#define DRM_IOCTL_MOD_CTX		DRM_IOW( 0x22, drm_ctx_t)#define DRM_IOCTL_GET_CTX		DRM_IOWR(0x23, drm_ctx_t)#define DRM_IOCTL_SWITCH_CTX		DRM_IOW( 0x24, drm_ctx_t)#define DRM_IOCTL_NEW_CTX		DRM_IOW( 0x25, drm_ctx_t)#define DRM_IOCTL_RES_CTX		DRM_IOWR(0x26, drm_ctx_res_t)#define DRM_IOCTL_ADD_DRAW		DRM_IOWR(0x27, drm_draw_t)#define DRM_IOCTL_RM_DRAW		DRM_IOWR(0x28, drm_draw_t)#define DRM_IOCTL_DMA			DRM_IOWR(0x29, drm_dma_t)#define DRM_IOCTL_LOCK			DRM_IOW( 0x2a, drm_lock_t)#define DRM_IOCTL_UNLOCK		DRM_IOW( 0x2b, drm_lock_t)#define DRM_IOCTL_FINISH		DRM_IOW( 0x2c, drm_lock_t)#define DRM_IOCTL_AGP_ACQUIRE		DRM_IO(  0x30)#define DRM_IOCTL_AGP_RELEASE		DRM_IO(  0x31)#define DRM_IOCTL_AGP_ENABLE		DRM_IOW( 0x32, drm_agp_mode_t)#define DRM_IOCTL_AGP_INFO		DRM_IOR( 0x33, drm_agp_info_t)#define DRM_IOCTL_AGP_ALLOC		DRM_IOWR(0x34, drm_agp_buffer_t)#define DRM_IOCTL_AGP_FREE		DRM_IOW( 0x35, drm_agp_buffer_t)#define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, drm_agp_binding_t)#define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, drm_agp_binding_t)/* Mga specific ioctls */#define DRM_IOCTL_MGA_INIT		DRM_IOW( 0x40, drm_mga_init_t)#define DRM_IOCTL_MGA_SWAP		DRM_IOW( 0x41, drm_mga_swap_t)#define DRM_IOCTL_MGA_CLEAR		DRM_IOW( 0x42, drm_mga_clear_t)#define DRM_IOCTL_MGA_ILOAD		DRM_IOW( 0x43, drm_mga_iload_t)#define DRM_IOCTL_MGA_VERTEX		DRM_IOW( 0x44, drm_mga_vertex_t)#define DRM_IOCTL_MGA_FLUSH		DRM_IOW( 0x45, drm_lock_t )#define DRM_IOCTL_MGA_INDICES		DRM_IOW( 0x46, drm_mga_indices_t)#define DRM_IOCTL_MGA_BLIT		DRM_IOW( 0x47, drm_mga_blit_t)/* I810 specific ioctls */#define DRM_IOCTL_I810_INIT		DRM_IOW( 0x40, drm_i810_init_t)#define DRM_IOCTL_I810_VERTEX		DRM_IOW( 0x41, drm_i810_vertex_t)#define DRM_IOCTL_I810_CLEAR		DRM_IOW( 0x42, drm_i810_clear_t)#define DRM_IOCTL_I810_FLUSH		DRM_IO(  0x43)#define DRM_IOCTL_I810_GETAGE		DRM_IO(  0x44)#define DRM_IOCTL_I810_GETBUF		DRM_IOWR(0x45, drm_i810_dma_t)#define DRM_IOCTL_I810_SWAP		DRM_IO(  0x46)#define DRM_IOCTL_I810_COPY		DRM_IOW( 0x47, drm_i810_copy_t)#define DRM_IOCTL_I810_DOCOPY		DRM_IO(  0x48)/* Rage 128 specific ioctls */#define DRM_IOCTL_R128_INIT		DRM_IOW( 0x40, drm_r128_init_t)#define DRM_IOCTL_R128_CCE_START	DRM_IO(  0x41)#define DRM_IOCTL_R128_CCE_STOP		DRM_IOW( 0x42, drm_r128_cce_stop_t)#define DRM_IOCTL_R128_CCE_RESET	DRM_IO(  0x43)#define DRM_IOCTL_R128_CCE_IDLE		DRM_IO(  0x44)#define DRM_IOCTL_R128_RESET		DRM_IO(  0x46)#define DRM_IOCTL_R128_SWAP		DRM_IO(  0x47)#define DRM_IOCTL_R128_CLEAR		DRM_IOW( 0x48, drm_r128_clear_t)#define DRM_IOCTL_R128_VERTEX		DRM_IOW( 0x49, drm_r128_vertex_t)#define DRM_IOCTL_R128_INDICES		DRM_IOW( 0x4a, drm_r128_indices_t)#define DRM_IOCTL_R128_BLIT		DRM_IOW( 0x4b, drm_r128_blit_t)#define DRM_IOCTL_R128_DEPTH		DRM_IOW( 0x4c, drm_r128_depth_t)#define DRM_IOCTL_R128_STIPPLE		DRM_IOW( 0x4d, drm_r128_stipple_t)#define DRM_IOCTL_R128_PACKET		DRM_IOWR(0x4e, drm_r128_packet_t)/* Radeon specific ioctls */#define DRM_IOCTL_RADEON_CP_INIT	DRM_IOW( 0x40, drm_radeon_init_t)#define DRM_IOCTL_RADEON_CP_START	DRM_IO(  0x41)#define DRM_IOCTL_RADEON_CP_STOP	DRM_IOW( 0x42, drm_radeon_cp_stop_t)#define DRM_IOCTL_RADEON_CP_RESET	DRM_IO(  0x43)#define DRM_IOCTL_RADEON_CP_IDLE	DRM_IO(  0x44)#define DRM_IOCTL_RADEON_RESET		DRM_IO(  0x45)#define DRM_IOCTL_RADEON_FULLSCREEN	DRM_IOW( 0x46, drm_radeon_fullscreen_t)#define DRM_IOCTL_RADEON_SWAP		DRM_IO(  0x47)#define DRM_IOCTL_RADEON_CLEAR		DRM_IOW( 0x48, drm_radeon_clear_t)#define DRM_IOCTL_RADEON_VERTEX		DRM_IOW( 0x49, drm_radeon_vertex_t)#define DRM_IOCTL_RADEON_INDICES	DRM_IOW( 0x4a, drm_radeon_indices_t)#define DRM_IOCTL_RADEON_BLIT		DRM_IOW( 0x4b, drm_radeon_blit_t)#define DRM_IOCTL_RADEON_STIPPLE	DRM_IOW( 0x4c, drm_radeon_stipple_t)#define DRM_IOCTL_RADEON_INDIRECT	DRM_IOWR(0x4d, drm_radeon_indirect_t)#ifdef CONFIG_DRM40_SIS/* SiS specific ioctls */#define SIS_IOCTL_FB_ALLOC		DRM_IOWR(0x44, drm_sis_mem_t)#define SIS_IOCTL_FB_FREE		DRM_IOW( 0x45, drm_sis_mem_t)#define SIS_IOCTL_AGP_INIT		DRM_IOWR(0x53, drm_sis_agp_t)#define SIS_IOCTL_AGP_ALLOC		DRM_IOWR(0x54, drm_sis_mem_t)#define SIS_IOCTL_AGP_FREE		DRM_IOW( 0x55, drm_sis_mem_t)#define SIS_IOCTL_FLIP			DRM_IOW( 0x48, drm_sis_flip_t)#define SIS_IOCTL_FLIP_INIT		DRM_IO(  0x49)#define SIS_IOCTL_FLIP_FINAL		DRM_IO(  0x50)#endif#endif