;/*
; *  ____________________________________________________________________
; * 
; *  Copyright (c) 2004, Andrew N. Sloss, Chris Wright and Dominic Symes
; *  All rights reserved.
; *  ____________________________________________________________________
; * 
; *  NON-COMMERCIAL USE License
; *  
; *  Redistribution and use in source and binary forms, with or without 
; *  modification, are permitted provided that the following conditions 
; *  are met: 
; *  
; *  1. For NON-COMMERCIAL USE only.
; * 
; *  2. Redistributions of source code must retain the above copyright 
; *     notice, this list of conditions and the following disclaimer. 
; * 
; *  3. Redistributions in binary form must reproduce the above 
; *     copyright notice, this list of conditions and the following 
; *     disclaimer in the documentation and/or other materials provided 
; *     with the distribution. 
; * 
; *  4. All advertising materials mentioning features or use of this 
; *     software must display the following acknowledgement:
; * 
; *     This product includes software developed by Andrew N. Sloss,
; *     Chris Wright and Dominic Symes. 
; * 
; *   THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS ``AS IS'' AND ANY 
; *   EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
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; */

;/***********************************************************************
; *
; *  Module       : vic.s
; *  Descriptions : Vector Interrupt Service Routine
; *  Example      : 9.10
; *  OS           : generic
; *  Platform     : generic
; *  History      :
; *
; *  31th December 2003
; *  - added header
; *
; ***********************************************************************/

     EXPORT vectorServiceRoutine

INTON          EQU 0x0000               ; enable interrupts
SYS32md        EQU 0x1f                 ; ***??? system mode 
IRQ32md        EQU 0x12                 ; system mode
I_Bit          EQU 0x80
VICBaseAddr    EQU 0xfffff000           ; base address of VIC controller
VICVectorAddr  EQU VICBaseAddr+0x30     ; isr address of interupt 

Maskmd		EQU 0x1f                ; processor mode mask
SVC32md		EQU 0x13                ; SVC mode

     AREA vic,CODE,readonly

vectorServiceRoutine
     SUB     r14,r14,#4                 ; r14-=4
     STMFD   r13!, {r0-r3,r12,r14}      ; save context
     MRS     r12, spsr                  ; copy spsr
     STMFD   r13!,{r12}                 ; save spsr
     MSR     cpsr_c, #INTON|SYS32md     ; cpsr_c=ift_system
     ; <insert code>
     MSR     cpsr_c, #I_Bit|IRQ32md     ; cpsr_c=Ift_irq
     LDMFD   r13!, {r12}                ; restore r12 (spsr_irq)
     MSR     spsr_cxsf, r12             ; restore spsr
     LDR     r1,=VICVectorAddr          ; load VectorAddress
     STR     r0, [r1]                   ; inform VIC interrupt serviced
     LDMFD   r13!, {r0-r3,r12,pc}^      ; return
     END