?? stm32f10x_adc.txt
字號:
; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_adc.o --depend=.\Obj\stm32f10x_adc.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c]
THUMB
AREA ||i.ADC_AnalogWatchdogCmd||, CODE, READONLY, ALIGN=2
ADC_AnalogWatchdogCmd PROC
;;;1080 */
;;;1081 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
000000 2200 MOVS r2,#0
;;;1082 {
;;;1083 uint32_t tmpreg = 0;
;;;1084 /* Check the parameters */
;;;1085 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1086 assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
;;;1087 /* Get the old register value */
;;;1088 tmpreg = ADCx->CR1;
000002 6842 LDR r2,[r0,#4]
;;;1089 /* Clear AWDEN, AWDENJ and AWDSGL bits */
;;;1090 tmpreg &= CR1_AWDMode_Reset;
000004 4b02 LDR r3,|L1.16|
000006 401a ANDS r2,r2,r3
;;;1091 /* Set the analog watchdog enable mode */
;;;1092 tmpreg |= ADC_AnalogWatchdog;
000008 430a ORRS r2,r2,r1
;;;1093 /* Store the new register value */
;;;1094 ADCx->CR1 = tmpreg;
00000a 6042 STR r2,[r0,#4]
;;;1095 }
00000c 4770 BX lr
;;;1096
ENDP
00000e 0000 DCW 0x0000
|L1.16|
DCD 0xff3ffdff
AREA ||i.ADC_AnalogWatchdogSingleChannelConfig||, CODE, READONLY, ALIGN=1
ADC_AnalogWatchdogSingleChannelConfig PROC
;;;1143 */
;;;1144 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
000000 2200 MOVS r2,#0
;;;1145 {
;;;1146 uint32_t tmpreg = 0;
;;;1147 /* Check the parameters */
;;;1148 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1149 assert_param(IS_ADC_CHANNEL(ADC_Channel));
;;;1150 /* Get the old register value */
;;;1151 tmpreg = ADCx->CR1;
000002 6842 LDR r2,[r0,#4]
;;;1152 /* Clear the Analog watchdog channel select bits */
;;;1153 tmpreg &= CR1_AWDCH_Reset;
000004 f022021f BIC r2,r2,#0x1f
;;;1154 /* Set the Analog watchdog channel */
;;;1155 tmpreg |= ADC_Channel;
000008 430a ORRS r2,r2,r1
;;;1156 /* Store the new register value */
;;;1157 ADCx->CR1 = tmpreg;
00000a 6042 STR r2,[r0,#4]
;;;1158 }
00000c 4770 BX lr
;;;1159
ENDP
AREA ||i.ADC_AnalogWatchdogThresholdsConfig||, CODE, READONLY, ALIGN=1
ADC_AnalogWatchdogThresholdsConfig PROC
;;;1105 */
;;;1106 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
000000 6241 STR r1,[r0,#0x24]
;;;1107 uint16_t LowThreshold)
;;;1108 {
;;;1109 /* Check the parameters */
;;;1110 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1111 assert_param(IS_ADC_THRESHOLD(HighThreshold));
;;;1112 assert_param(IS_ADC_THRESHOLD(LowThreshold));
;;;1113 /* Set the ADCx high threshold */
;;;1114 ADCx->HTR = HighThreshold;
;;;1115 /* Set the ADCx low threshold */
;;;1116 ADCx->LTR = LowThreshold;
000002 6282 STR r2,[r0,#0x28]
;;;1117 }
000004 4770 BX lr
;;;1118
ENDP
AREA ||i.ADC_AutoInjectedConvCmd||, CODE, READONLY, ALIGN=1
ADC_AutoInjectedConvCmd PROC
;;;732 */
;;;733 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000 b121 CBZ r1,|L4.12|
;;;734 {
;;;735 /* Check the parameters */
;;;736 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;737 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;738 if (NewState != DISABLE)
;;;739 {
;;;740 /* Enable the selected ADC automatic injected group conversion */
;;;741 ADCx->CR1 |= CR1_JAUTO_Set;
000002 6842 LDR r2,[r0,#4]
000004 f4426280 ORR r2,r2,#0x400
000008 6042 STR r2,[r0,#4]
00000a e003 B |L4.20|
|L4.12|
;;;742 }
;;;743 else
;;;744 {
;;;745 /* Disable the selected ADC automatic injected group conversion */
;;;746 ADCx->CR1 &= CR1_JAUTO_Reset;
00000c 6842 LDR r2,[r0,#4]
00000e f4226280 BIC r2,r2,#0x400
000012 6042 STR r2,[r0,#4]
|L4.20|
;;;747 }
;;;748 }
000014 4770 BX lr
;;;749
ENDP
AREA ||i.ADC_ClearFlag||, CODE, READONLY, ALIGN=1
ADC_ClearFlag PROC
;;;1226 */
;;;1227 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
000000 43ca MVNS r2,r1
;;;1228 {
;;;1229 /* Check the parameters */
;;;1230 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1231 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
;;;1232 /* Clear the selected ADC flags */
;;;1233 ADCx->SR = ~(uint32_t)ADC_FLAG;
000002 6002 STR r2,[r0,#0]
;;;1234 }
000004 4770 BX lr
;;;1235
ENDP
AREA ||i.ADC_ClearITPendingBit||, CODE, READONLY, ALIGN=1
ADC_ClearITPendingBit PROC
;;;1281 */
;;;1282 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
000000 2200 MOVS r2,#0
;;;1283 {
;;;1284 uint8_t itmask = 0;
;;;1285 /* Check the parameters */
;;;1286 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1287 assert_param(IS_ADC_IT(ADC_IT));
;;;1288 /* Get the ADC IT index */
;;;1289 itmask = (uint8_t)(ADC_IT >> 8);
000002 120a ASRS r2,r1,#8
;;;1290 /* Clear the selected ADC interrupt pending bits */
;;;1291 ADCx->SR = ~(uint32_t)itmask;
000004 43d3 MVNS r3,r2
000006 6003 STR r3,[r0,#0]
;;;1292 }
000008 4770 BX lr
;;;1293
ENDP
AREA ||i.ADC_Cmd||, CODE, READONLY, ALIGN=1
ADC_Cmd PROC
;;;297 */
;;;298 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000 b121 CBZ r1,|L7.12|
;;;299 {
;;;300 /* Check the parameters */
;;;301 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;302 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;303 if (NewState != DISABLE)
;;;304 {
;;;305 /* Set the ADON bit to wake up the ADC from power down mode */
;;;306 ADCx->CR2 |= CR2_ADON_Set;
000002 6882 LDR r2,[r0,#8]
000004 f0420201 ORR r2,r2,#1
000008 6082 STR r2,[r0,#8]
00000a e003 B |L7.20|
|L7.12|
;;;307 }
;;;308 else
;;;309 {
;;;310 /* Disable the selected ADC peripheral */
;;;311 ADCx->CR2 &= CR2_ADON_Reset;
00000c 6882 LDR r2,[r0,#8]
00000e f0220201 BIC r2,r2,#1
000012 6082 STR r2,[r0,#8]
|L7.20|
;;;312 }
;;;313 }
000014 4770 BX lr
;;;314
ENDP
AREA ||i.ADC_DMACmd||, CODE, READONLY, ALIGN=1
ADC_DMACmd PROC
;;;322 */
;;;323 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000 b121 CBZ r1,|L8.12|
;;;324 {
;;;325 /* Check the parameters */
;;;326 assert_param(IS_ADC_DMA_PERIPH(ADCx));
;;;327 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;328 if (NewState != DISABLE)
;;;329 {
;;;330 /* Enable the selected ADC DMA request */
;;;331 ADCx->CR2 |= CR2_DMA_Set;
000002 6882 LDR r2,[r0,#8]
000004 f4427280 ORR r2,r2,#0x100
000008 6082 STR r2,[r0,#8]
00000a e003 B |L8.20|
|L8.12|
;;;332 }
;;;333 else
;;;334 {
;;;335 /* Disable the selected ADC DMA request */
;;;336 ADCx->CR2 &= CR2_DMA_Reset;
00000c 6882 LDR r2,[r0,#8]
00000e f4227280 BIC r2,r2,#0x100
000012 6082 STR r2,[r0,#8]
|L8.20|
;;;337 }
;;;338 }
000014 4770 BX lr
;;;339
ENDP
AREA ||i.ADC_DeInit||, CODE, READONLY, ALIGN=2
ADC_DeInit PROC
;;;177 */
;;;178 void ADC_DeInit(ADC_TypeDef* ADCx)
000000 b510 PUSH {r4,lr}
;;;179 {
000002 4604 MOV r4,r0
;;;180 /* Check the parameters */
;;;181 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;182
;;;183 if (ADCx == ADC1)
000004 4812 LDR r0,|L9.80|
000006 4284 CMP r4,r0
000008 d108 BNE |L9.28|
;;;184 {
;;;185 /* Enable ADC1 reset state */
;;;186 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
00000a 2101 MOVS r1,#1
00000c 1540 ASRS r0,r0,#21
00000e f7fffffe BL RCC_APB2PeriphResetCmd
;;;187 /* Release ADC1 from reset state */
;;;188 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
000012 2100 MOVS r1,#0
000014 1560 ASRS r0,r4,#21
000016 f7fffffe BL RCC_APB2PeriphResetCmd
00001a e017 B |L9.76|
|L9.28|
;;;189 }
;;;190 else if (ADCx == ADC2)
00001c 480d LDR r0,|L9.84|
00001e 4284 CMP r4,r0
000020 d108 BNE |L9.52|
;;;191 {
;;;192 /* Enable ADC2 reset state */
;;;193 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
000022 2101 MOVS r1,#1
000024 1500 ASRS r0,r0,#20
000026 f7fffffe BL RCC_APB2PeriphResetCmd
;;;194 /* Release ADC2 from reset state */
;;;195 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
00002a 2100 MOVS r1,#0
00002c 1520 ASRS r0,r4,#20
00002e f7fffffe BL RCC_APB2PeriphResetCmd
000032 e00b B |L9.76|
|L9.52|
;;;196 }
;;;197 else
;;;198 {
;;;199 if (ADCx == ADC3)
000034 4808 LDR r0,|L9.88|
000036 4284 CMP r4,r0
000038 d108 BNE |L9.76|
;;;200 {
;;;201 /* Enable ADC3 reset state */
;;;202 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);
00003a 2101 MOVS r1,#1
00003c 03c8 LSLS r0,r1,#15
00003e f7fffffe BL RCC_APB2PeriphResetCmd
;;;203 /* Release ADC3 from reset state */
;;;204 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);
000042 2100 MOVS r1,#0
000044 f44f4000 MOV r0,#0x8000
000048 f7fffffe BL RCC_APB2PeriphResetCmd
|L9.76|
;;;205 }
;;;206 }
;;;207 }
00004c bd10 POP {r4,pc}
;;;208
ENDP
00004e 0000 DCW 0x0000
|L9.80|
DCD 0x40012400
|L9.84|
DCD 0x40012800
|L9.88|
DCD 0x40013c00
AREA ||i.ADC_DiscModeChannelCountConfig||, CODE, READONLY, ALIGN=1
ADC_DiscModeChannelCountConfig PROC
;;;507 */
;;;508 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
000000 b510 PUSH {r4,lr}
;;;509 {
;;;510 uint32_t tmpreg1 = 0;
000002 2200 MOVS r2,#0
;;;511 uint32_t tmpreg2 = 0;
000004 2300 MOVS r3,#0
;;;512 /* Check the parameters */
;;;513 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;514 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
;;;515 /* Get the old register value */
;;;516 tmpreg1 = ADCx->CR1;
000006 6842 LDR r2,[r0,#4]
;;;517 /* Clear the old discontinuous mode channel count */
;;;518 tmpreg1 &= CR1_DISCNUM_Reset;
000008 f4224260 BIC r2,r2,#0xe000
;;;519 /* Set the discontinuous mode channel count */
;;;520 tmpreg2 = Number - 1;
00000c 1e4b SUBS r3,r1,#1
;;;521 tmpreg1 |= tmpreg2 << 13;
00000e ea423243 ORR r2,r2,r3,LSL #13
;;;522 /* Store the new register value */
;;;523 ADCx->CR1 = tmpreg1;
000012 6042 STR r2,[r0,#4]
;;;524 }
000014 bd10 POP {r4,pc}
;;;525
ENDP
AREA ||i.ADC_DiscModeCmd||, CODE, READONLY, ALIGN=1
ADC_DiscModeCmd PROC
;;;534 */
;;;535 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000 b121 CBZ r1,|L11.12|
;;;536 {
;;;537 /* Check the parameters */
;;;538 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;539 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;540 if (NewState != DISABLE)
;;;541 {
;;;542 /* Enable the selected ADC regular discontinuous mode */
;;;543 ADCx->CR1 |= CR1_DISCEN_Set;
000002 6842 LDR r2,[r0,#4]
000004 f4426200 ORR r2,r2,#0x800
000008 6042 STR r2,[r0,#4]
00000a e003 B |L11.20|
|L11.12|
;;;544 }
;;;545 else
;;;546 {
;;;547 /* Disable the selected ADC regular discontinuous mode */
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