?? stm32f10x_adc.txt
字號:
000010 2000 MOVS r0,#0
|L22.18|
;;;495 }
;;;496 /* Return the SWSTART bit status */
;;;497 return bitstatus;
;;;498 }
000012 4770 BX lr
;;;499
ENDP
AREA ||i.ADC_GetSoftwareStartInjectedConvCmdStatus||, CODE, READONLY, ALIGN=1
ADC_GetSoftwareStartInjectedConvCmdStatus PROC
;;;871 */
;;;872 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
000000 4601 MOV r1,r0
;;;873 {
;;;874 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;875 /* Check the parameters */
;;;876 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;877 /* Check the status of JSWSTART bit */
;;;878 if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)
000004 688a LDR r2,[r1,#8]
000006 f4121f00 TST r2,#0x200000
00000a d001 BEQ |L23.16|
;;;879 {
;;;880 /* JSWSTART bit is set */
;;;881 bitstatus = SET;
00000c 2001 MOVS r0,#1
00000e e000 B |L23.18|
|L23.16|
;;;882 }
;;;883 else
;;;884 {
;;;885 /* JSWSTART bit is reset */
;;;886 bitstatus = RESET;
000010 2000 MOVS r0,#0
|L23.18|
;;;887 }
;;;888 /* Return the JSWSTART bit status */
;;;889 return bitstatus;
;;;890 }
000012 4770 BX lr
;;;891
ENDP
AREA ||i.ADC_ITConfig||, CODE, READONLY, ALIGN=1
ADC_ITConfig PROC
;;;351 */
;;;352 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
000000 b510 PUSH {r4,lr}
;;;353 {
;;;354 uint8_t itmask = 0;
000002 2300 MOVS r3,#0
;;;355 /* Check the parameters */
;;;356 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;357 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;358 assert_param(IS_ADC_IT(ADC_IT));
;;;359 /* Get the ADC IT index */
;;;360 itmask = (uint8_t)ADC_IT;
000004 b2cb UXTB r3,r1
;;;361 if (NewState != DISABLE)
000006 b11a CBZ r2,|L24.16|
;;;362 {
;;;363 /* Enable the selected ADC interrupts */
;;;364 ADCx->CR1 |= itmask;
000008 6844 LDR r4,[r0,#4]
00000a 431c ORRS r4,r4,r3
00000c 6044 STR r4,[r0,#4]
00000e e002 B |L24.22|
|L24.16|
;;;365 }
;;;366 else
;;;367 {
;;;368 /* Disable the selected ADC interrupts */
;;;369 ADCx->CR1 &= (~(uint32_t)itmask);
000010 6844 LDR r4,[r0,#4]
000012 439c BICS r4,r4,r3
000014 6044 STR r4,[r0,#4]
|L24.22|
;;;370 }
;;;371 }
000016 bd10 POP {r4,pc}
;;;372
ENDP
AREA ||i.ADC_Init||, CODE, READONLY, ALIGN=2
ADC_Init PROC
;;;216 */
;;;217 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
000000 b530 PUSH {r4,r5,lr}
;;;218 {
;;;219 uint32_t tmpreg1 = 0;
000002 2200 MOVS r2,#0
;;;220 uint8_t tmpreg2 = 0;
000004 2300 MOVS r3,#0
;;;221 /* Check the parameters */
;;;222 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;223 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
;;;224 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
;;;225 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
;;;226 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
;;;227 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
;;;228 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
;;;229
;;;230 /*---------------------------- ADCx CR1 Configuration -----------------*/
;;;231 /* Get the ADCx CR1 value */
;;;232 tmpreg1 = ADCx->CR1;
000006 6842 LDR r2,[r0,#4]
;;;233 /* Clear DUALMOD and SCAN bits */
;;;234 tmpreg1 &= CR1_CLEAR_Mask;
000008 4c0e LDR r4,|L25.68|
00000a 4022 ANDS r2,r2,r4
;;;235 /* Configure ADCx: Dual mode and scan conversion mode */
;;;236 /* Set DUALMOD bits according to ADC_Mode value */
;;;237 /* Set SCAN bit according to ADC_ScanConvMode value */
;;;238 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
00000c 790d LDRB r5,[r1,#4]
00000e 680c LDR r4,[r1,#0]
000010 ea442405 ORR r4,r4,r5,LSL #8
000014 4322 ORRS r2,r2,r4
;;;239 /* Write to ADCx CR1 */
;;;240 ADCx->CR1 = tmpreg1;
000016 6042 STR r2,[r0,#4]
;;;241
;;;242 /*---------------------------- ADCx CR2 Configuration -----------------*/
;;;243 /* Get the ADCx CR2 value */
;;;244 tmpreg1 = ADCx->CR2;
000018 6882 LDR r2,[r0,#8]
;;;245 /* Clear CONT, ALIGN and EXTSEL bits */
;;;246 tmpreg1 &= CR2_CLEAR_Mask;
00001a 4c0b LDR r4,|L25.72|
00001c 4022 ANDS r2,r2,r4
;;;247 /* Configure ADCx: external trigger event and continuous conversion mode */
;;;248 /* Set ALIGN bit according to ADC_DataAlign value */
;;;249 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
;;;250 /* Set CONT bit according to ADC_ContinuousConvMode value */
;;;251 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
00001e e9d15402 LDRD r5,r4,[r1,#8]
000022 432c ORRS r4,r4,r5
000024 794d LDRB r5,[r1,#5]
000026 ea440445 ORR r4,r4,r5,LSL #1
00002a 4322 ORRS r2,r2,r4
;;;252 ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
;;;253 /* Write to ADCx CR2 */
;;;254 ADCx->CR2 = tmpreg1;
00002c 6082 STR r2,[r0,#8]
;;;255
;;;256 /*---------------------------- ADCx SQR1 Configuration -----------------*/
;;;257 /* Get the ADCx SQR1 value */
;;;258 tmpreg1 = ADCx->SQR1;
00002e 6ac2 LDR r2,[r0,#0x2c]
;;;259 /* Clear L bits */
;;;260 tmpreg1 &= SQR1_CLEAR_Mask;
000030 f4220270 BIC r2,r2,#0xf00000
;;;261 /* Configure ADCx: regular channel sequence length */
;;;262 /* Set L bits according to ADC_NbrOfChannel value */
;;;263 tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
000034 7c0c LDRB r4,[r1,#0x10]
000036 1e64 SUBS r4,r4,#1
000038 b2e4 UXTB r4,r4
00003a 4323 ORRS r3,r3,r4
;;;264 tmpreg1 |= (uint32_t)tmpreg2 << 20;
00003c ea425203 ORR r2,r2,r3,LSL #20
;;;265 /* Write to ADCx SQR1 */
;;;266 ADCx->SQR1 = tmpreg1;
000040 62c2 STR r2,[r0,#0x2c]
;;;267 }
000042 bd30 POP {r4,r5,pc}
;;;268
ENDP
|L25.68|
DCD 0xfff0feff
|L25.72|
DCD 0xfff1f7fd
AREA ||i.ADC_InjectedChannelConfig||, CODE, READONLY, ALIGN=1
ADC_InjectedChannelConfig PROC
;;;928 */
;;;929 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
000000 b5f0 PUSH {r4-r7,lr}
;;;930 {
;;;931 uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
000006 2600 MOVS r6,#0
;;;932 /* Check the parameters */
;;;933 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;934 assert_param(IS_ADC_CHANNEL(ADC_Channel));
;;;935 assert_param(IS_ADC_INJECTED_RANK(Rank));
;;;936 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;937 /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;938 if (ADC_Channel > ADC_Channel_9)
000008 2909 CMP r1,#9
00000a dd11 BLE |L26.48|
;;;939 {
;;;940 /* Get the old register value */
;;;941 tmpreg1 = ADCx->SMPR1;
00000c 68c4 LDR r4,[r0,#0xc]
;;;942 /* Calculate the mask to clear */
;;;943 tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
00000e f1a1070a SUB r7,r1,#0xa
000012 eb070c47 ADD r12,r7,r7,LSL #1
000016 2707 MOVS r7,#7
000018 fa07f50c LSL r5,r7,r12
;;;944 /* Clear the old channel sample time */
;;;945 tmpreg1 &= ~tmpreg2;
00001c 43ac BICS r4,r4,r5
;;;946 /* Calculate the mask to set */
;;;947 tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
00001e f1a1070a SUB r7,r1,#0xa
000022 eb070747 ADD r7,r7,r7,LSL #1
000026 fa03f507 LSL r5,r3,r7
;;;948 /* Set the new channel sample time */
;;;949 tmpreg1 |= tmpreg2;
00002a 432c ORRS r4,r4,r5
;;;950 /* Store the new register value */
;;;951 ADCx->SMPR1 = tmpreg1;
00002c 60c4 STR r4,[r0,#0xc]
00002e e00c B |L26.74|
|L26.48|
;;;952 }
;;;953 else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;954 {
;;;955 /* Get the old register value */
;;;956 tmpreg1 = ADCx->SMPR2;
000030 6904 LDR r4,[r0,#0x10]
;;;957 /* Calculate the mask to clear */
;;;958 tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
000032 eb010c41 ADD r12,r1,r1,LSL #1
000036 2707 MOVS r7,#7
000038 fa07f50c LSL r5,r7,r12
;;;959 /* Clear the old channel sample time */
;;;960 tmpreg1 &= ~tmpreg2;
00003c 43ac BICS r4,r4,r5
;;;961 /* Calculate the mask to set */
;;;962 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
00003e eb010741 ADD r7,r1,r1,LSL #1
000042 fa03f507 LSL r5,r3,r7
;;;963 /* Set the new channel sample time */
;;;964 tmpreg1 |= tmpreg2;
000046 432c ORRS r4,r4,r5
;;;965 /* Store the new register value */
;;;966 ADCx->SMPR2 = tmpreg1;
000048 6104 STR r4,[r0,#0x10]
|L26.74|
;;;967 }
;;;968 /* Rank configuration */
;;;969 /* Get the old register value */
;;;970 tmpreg1 = ADCx->JSQR;
00004a 6b84 LDR r4,[r0,#0x38]
;;;971 /* Get JL value: Number = JL+1 */
;;;972 tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;
00004c f3c45601 UBFX r6,r4,#20,#2
;;;973 /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
;;;974 tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
000050 1cd7 ADDS r7,r2,#3
000052 f1060c01 ADD r12,r6,#1
000056 eba7070c SUB r7,r7,r12
00005a eb070c87 ADD r12,r7,r7,LSL #2
00005e 271f MOVS r7,#0x1f
000060 fa07f50c LSL r5,r7,r12
;;;975 /* Clear the old JSQx bits for the selected rank */
;;;976 tmpreg1 &= ~tmpreg2;
000064 43ac BICS r4,r4,r5
;;;977 /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;978 tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
000066 1cd7 ADDS r7,r2,#3
000068 f1060c01 ADD r12,r6,#1
00006c eba7070c SUB r7,r7,r12
000070 eb070787 ADD r7,r7,r7,LSL #2
000074 fa01f507 LSL r5,r1,r7
;;;979 /* Set the JSQx bits for the selected rank */
;;;980 tmpreg1 |= tmpreg2;
000078 432c ORRS r4,r4,r5
;;;981 /* Store the new register value */
;;;982 ADCx->JSQR = tmpreg1;
00007a 6384 STR r4,[r0,#0x38]
;;;983 }
00007c bdf0 POP {r4-r7,pc}
;;;984
ENDP
AREA ||i.ADC_InjectedDiscModeCmd||, CODE, READONLY, ALIGN=1
ADC_InjectedDiscModeCmd PROC
;;;758 */
;;;759 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000 b121 CBZ r1,|L27.12|
;;;760 {
;;;761 /* Check the parameters */
;;;762 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;763 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;764 if (NewState != DISABLE)
;;;765 {
;;;766 /* Enable the selected ADC injected discontinuous mode */
;;;767 ADCx->CR1 |= CR1_JDISCEN_Set;
000002 6842 LDR r2,[r0,#4]
000004 f4425280 ORR r2,r2,#0x1000
000008 6042 STR r2,[r0,#4]
00000a e003 B |L27.20|
|L27.12|
;;;768 }
;;;769 else
;;;770 {
;;;771 /* Disable the selected ADC injected discontinuous mode */
;;;772 ADCx->CR1 &= CR1_JDISCEN_Reset;
00000c 6842 LDR r2,[r0,#4]
00000e f4225280 BIC r2,r2,#0x1000
000012 6042 STR r2,[r0,#4]
|L27.20|
;;;773 }
;;;774 }
000014 4770 BX lr
;;;775
ENDP
AREA ||i.ADC_InjectedSequencerLengthConfig||, CODE, READONLY, ALIGN=1
ADC_InjectedSequencerLengthConfig PROC
;;;991 */
;;;992 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
000000 b510 PUSH {r4,lr}
;;;993 {
;;;994 uint32_t tmpreg1 = 0;
000002 2200 MOVS r2,#0
;;;995 uint32_t tmpreg2 = 0;
000004 2300 MOVS r3,#0
;;;996 /* Check the parameters */
;;;997 assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;998 assert_param(IS_ADC_INJECTED_LENGTH(Length));
;;;999
;;;1000 /* Get the old register value */
;;;1001 tmpreg1 = ADCx->JSQR;
000006 6b82 LDR r2,[r0,#0x38]
;;;1002 /* Clear the old injected sequnence lenght JL bits */
;;;1003 tmpreg1 &= JSQR_JL_Reset;
000008 f4221240 BIC r2,r2,#0x300000
;;;1004 /* Set the injected sequnence lenght JL bits */
;;;1005 tmpreg2 = Length - 1;
00000c 1e4b SUBS r3,r1,#1
;;;1006 tmpreg1 |= tmpreg2 << 20;
00000e ea425203 ORR r2,r2,r3,LSL #20
;;;1007 /* Store the new register value */
;;;1008 ADCx->JSQR = tmpreg1;
000012 6382 STR r2,[r0,#0x38]
;;;1009 }
000014 bd10 POP {r4,pc}
;;;1010
ENDP
AREA ||i.ADC_RegularChannelConfig||, CODE, READONLY, ALIGN=1
ADC_RegularChannelConfig PROC
;;;588 */
;;;589 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
000000 b5f0 PUSH {r4-r7,lr}
;;;590 {
;;;591 uint32_t tmpreg1 = 0, tmpreg2 = 0;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
;;;592 /* Check the parameters */
;;;593 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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