?? system_stm32f10x.txt
字號:
; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\system_stm32f10x.o --depend=.\Obj\system_stm32f10x.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\CMSIS\Core\CM3\system_stm32f10x.c]
THUMB
AREA ||i.SetSysClock||, CODE, READONLY, ALIGN=1
SetSysClock PROC
;;;233 */
;;;234 static void SetSysClock(void)
000000 b510 PUSH {r4,lr}
;;;235 {
;;;236 #ifdef SYSCLK_FREQ_HSE
;;;237 SetSysClockToHSE();
;;;238 #elif defined SYSCLK_FREQ_24MHz
;;;239 SetSysClockTo24();
;;;240 #elif defined SYSCLK_FREQ_36MHz
;;;241 SetSysClockTo36();
;;;242 #elif defined SYSCLK_FREQ_48MHz
;;;243 SetSysClockTo48();
;;;244 #elif defined SYSCLK_FREQ_56MHz
;;;245 SetSysClockTo56();
;;;246 #elif defined SYSCLK_FREQ_72MHz
;;;247 SetSysClockTo72();
000002 f7fffffe BL SetSysClockTo72
;;;248 #endif
;;;249
;;;250 /* If none of the define above is enabled, the HSI is used as System clock
;;;251 source (default after reset) */
;;;252 }
000006 bd10 POP {r4,pc}
;;;253
ENDP
AREA ||i.SetSysClockTo72||, CODE, READONLY, ALIGN=2
SetSysClockTo72 PROC
;;;817 */
;;;818 static void SetSysClockTo72(void)
000000 2000 MOVS r0,#0
;;;819 {
;;;820 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
000002 2100 MOVS r1,#0
;;;821
;;;822 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
;;;823 /* Enable HSE */
;;;824 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
000004 4a30 LDR r2,|L2.200|
000006 6812 LDR r2,[r2,#0]
000008 f4423280 ORR r2,r2,#0x10000
00000c 4b2e LDR r3,|L2.200|
00000e 601a STR r2,[r3,#0]
;;;825
;;;826 /* Wait till HSE is ready and if Time out is reached exit */
;;;827 do
000010 bf00 NOP
|L2.18|
;;;828 {
;;;829 HSEStatus = RCC->CR & RCC_CR_HSERDY;
000012 4a2d LDR r2,|L2.200|
000014 6812 LDR r2,[r2,#0]
000016 f4023100 AND r1,r2,#0x20000
;;;830 StartUpCounter++;
00001a 1c40 ADDS r0,r0,#1
;;;831 } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
00001c b911 CBNZ r1,|L2.36|
00001e f5b06fa0 CMP r0,#0x500
000022 d1f6 BNE |L2.18|
|L2.36|
;;;832
;;;833 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
000024 4a28 LDR r2,|L2.200|
000026 6812 LDR r2,[r2,#0]
000028 f4123f00 TST r2,#0x20000
00002c d001 BEQ |L2.50|
;;;834 {
;;;835 HSEStatus = (uint32_t)0x01;
00002e 2101 MOVS r1,#1
000030 e000 B |L2.52|
|L2.50|
;;;836 }
;;;837 else
;;;838 {
;;;839 HSEStatus = (uint32_t)0x00;
000032 2100 MOVS r1,#0
|L2.52|
;;;840 }
;;;841
;;;842 if (HSEStatus == (uint32_t)0x01)
000034 2901 CMP r1,#1
000036 d143 BNE |L2.192|
;;;843 {
;;;844 /* Enable Prefetch Buffer */
;;;845 FLASH->ACR |= FLASH_ACR_PRFTBE;
000038 4a24 LDR r2,|L2.204|
00003a 6812 LDR r2,[r2,#0]
00003c f0420210 ORR r2,r2,#0x10
000040 4b22 LDR r3,|L2.204|
000042 601a STR r2,[r3,#0]
;;;846
;;;847 /* Flash 2 wait state */
;;;848 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
000044 461a MOV r2,r3
000046 6812 LDR r2,[r2,#0]
000048 f0220203 BIC r2,r2,#3
00004c 601a STR r2,[r3,#0]
;;;849 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
00004e 461a MOV r2,r3
000050 6812 LDR r2,[r2,#0]
000052 f0420202 ORR r2,r2,#2
000056 601a STR r2,[r3,#0]
;;;850
;;;851
;;;852 /* HCLK = SYSCLK */
;;;853 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
000058 4a1b LDR r2,|L2.200|
00005a 6852 LDR r2,[r2,#4]
00005c 4b1a LDR r3,|L2.200|
00005e 605a STR r2,[r3,#4]
;;;854
;;;855 /* PCLK2 = HCLK */
;;;856 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
000060 461a MOV r2,r3
000062 6852 LDR r2,[r2,#4]
000064 605a STR r2,[r3,#4]
;;;857
;;;858 /* PCLK1 = HCLK/2 */
;;;859 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
000066 461a MOV r2,r3
000068 6852 LDR r2,[r2,#4]
00006a f4426280 ORR r2,r2,#0x400
00006e 605a STR r2,[r3,#4]
;;;860
;;;861 #ifdef STM32F10X_CL
;;;862 /* Configure PLLs ------------------------------------------------------*/
;;;863 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
;;;864 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
;;;865
;;;866 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
;;;867 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
;;;868 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
;;;869 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
;;;870
;;;871 /* Enable PLL2 */
;;;872 RCC->CR |= RCC_CR_PLL2ON;
;;;873 /* Wait till PLL2 is ready */
;;;874 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
;;;875 {
;;;876 }
;;;877
;;;878
;;;879 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
;;;880 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
;;;881 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
;;;882 RCC_CFGR_PLLMULL9);
;;;883 #else
;;;884 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
;;;885 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
000070 461a MOV r2,r3
000072 6852 LDR r2,[r2,#4]
000074 f422127c BIC r2,r2,#0x3f0000
000078 605a STR r2,[r3,#4]
;;;886 RCC_CFGR_PLLMULL));
;;;887 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
00007a 461a MOV r2,r3
00007c 6852 LDR r2,[r2,#4]
00007e f44212e8 ORR r2,r2,#0x1d0000
000082 605a STR r2,[r3,#4]
;;;888 #endif /* STM32F10X_CL */
;;;889
;;;890 /* Enable PLL */
;;;891 RCC->CR |= RCC_CR_PLLON;
000084 461a MOV r2,r3
000086 6812 LDR r2,[r2,#0]
000088 f0427280 ORR r2,r2,#0x1000000
00008c 601a STR r2,[r3,#0]
;;;892
;;;893 /* Wait till PLL is ready */
;;;894 while((RCC->CR & RCC_CR_PLLRDY) == 0)
00008e bf00 NOP
|L2.144|
000090 4a0d LDR r2,|L2.200|
000092 6812 LDR r2,[r2,#0]
000094 f0127f00 TST r2,#0x2000000
000098 d0fa BEQ |L2.144|
;;;895 {
;;;896 }
;;;897
;;;898 /* Select PLL as system clock source */
;;;899 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00009a 4a0b LDR r2,|L2.200|
00009c 6852 LDR r2,[r2,#4]
00009e f0220203 BIC r2,r2,#3
0000a2 4b09 LDR r3,|L2.200|
0000a4 605a STR r2,[r3,#4]
;;;900 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
0000a6 461a MOV r2,r3
0000a8 6852 LDR r2,[r2,#4]
0000aa f0420202 ORR r2,r2,#2
0000ae 605a STR r2,[r3,#4]
;;;901
;;;902 /* Wait till PLL is used as system clock source */
;;;903 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
0000b0 bf00 NOP
|L2.178|
0000b2 4a05 LDR r2,|L2.200|
0000b4 6852 LDR r2,[r2,#4]
0000b6 f002020c AND r2,r2,#0xc
0000ba 2a08 CMP r2,#8
0000bc d1f9 BNE |L2.178|
0000be e001 B |L2.196|
|L2.192|
;;;904 {
;;;905 }
;;;906 }
;;;907 else
;;;908 { /* If HSE fails to start-up, the application will have wrong clock
;;;909 configuration. User can add here some code to deal with this error */
;;;910
;;;911 /* Go to infinite loop */
;;;912 while (1)
0000c0 bf00 NOP
|L2.194|
0000c2 e7fe B |L2.194|
|L2.196|
;;;913 {
;;;914 }
;;;915 }
;;;916 }
0000c4 4770 BX lr
;;;917 #endif
ENDP
0000c6 0000 DCW 0x0000
|L2.200|
DCD 0x40021000
|L2.204|
DCD 0x40022000
AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2
SystemInit PROC
;;;186 */
;;;187 void SystemInit (void)
000000 b510 PUSH {r4,lr}
;;;188 {
;;;189 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
;;;190 /* Set HSION bit */
;;;191 RCC->CR |= (uint32_t)0x00000001;
000002 4811 LDR r0,|L3.72|
000004 6800 LDR r0,[r0,#0]
000006 f0400001 ORR r0,r0,#1
00000a 490f LDR r1,|L3.72|
00000c 6008 STR r0,[r1,#0]
;;;192
;;;193 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
;;;194 #ifndef STM32F10X_CL
;;;195 RCC->CFGR &= (uint32_t)0xF8FF0000;
00000e 4608 MOV r0,r1
000010 6840 LDR r0,[r0,#4]
000012 490e LDR r1,|L3.76|
000014 4008 ANDS r0,r0,r1
000016 490c LDR r1,|L3.72|
000018 6048 STR r0,[r1,#4]
;;;196 #else
;;;197 RCC->CFGR &= (uint32_t)0xF0FF0000;
;;;198 #endif /* STM32F10X_CL */
;;;199
;;;200 /* Reset HSEON, CSSON and PLLON bits */
;;;201 RCC->CR &= (uint32_t)0xFEF6FFFF;
00001a 4608 MOV r0,r1
00001c 6800 LDR r0,[r0,#0]
00001e 490c LDR r1,|L3.80|
000020 4008 ANDS r0,r0,r1
000022 4909 LDR r1,|L3.72|
000024 6008 STR r0,[r1,#0]
;;;202
;;;203 /* Reset HSEBYP bit */
;;;204 RCC->CR &= (uint32_t)0xFFFBFFFF;
000026 4608 MOV r0,r1
000028 6800 LDR r0,[r0,#0]
00002a f4202080 BIC r0,r0,#0x40000
00002e 6008 STR r0,[r1,#0]
;;;205
;;;206 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
;;;207 RCC->CFGR &= (uint32_t)0xFF80FFFF;
000030 4608 MOV r0,r1
000032 6840 LDR r0,[r0,#4]
000034 f42000fe BIC r0,r0,#0x7f0000
000038 6048 STR r0,[r1,#4]
;;;208
;;;209 #ifndef STM32F10X_CL
;;;210 /* Disable all interrupts and clear pending bits */
;;;211 RCC->CIR = 0x009F0000;
00003a f44f001f MOV r0,#0x9f0000
00003e 6088 STR r0,[r1,#8]
;;;212 #else
;;;213 /* Reset PLL2ON and PLL3ON bits */
;;;214 RCC->CR &= (uint32_t)0xEBFFFFFF;
;;;215
;;;216 /* Disable all interrupts and clear pending bits */
;;;217 RCC->CIR = 0x00FF0000;
;;;218
;;;219 /* Reset CFGR2 register */
;;;220 RCC->CFGR2 = 0x00000000;
;;;221 #endif /* STM32F10X_CL */
;;;222
;;;223 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
;;;224 /* Configure the Flash Latency cycles and enable prefetch buffer */
;;;225 SetSysClock();
000040 f7fffffe BL SetSysClock
;;;226
;;;227 }
000044 bd10 POP {r4,pc}
;;;228
ENDP
000046 0000 DCW 0x0000
|L3.72|
DCD 0x40021000
|L3.76|
DCD 0xf8ff0000
|L3.80|
DCD 0xfef6ffff
AREA ||.constdata||, DATA, READONLY, ALIGN=2
SystemFrequency
DCD 0x044aa200
SystemFrequency_SysClk
DCD 0x044aa200
SystemFrequency_AHBClk
DCD 0x044aa200
SystemFrequency_APB1Clk
DCD 0x02255100
SystemFrequency_APB2Clk
DCD 0x044aa200
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