?? stm32f10x_rcc.txt
字號:
; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_rcc.o --depend=.\Obj\stm32f10x_rcc.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c]
THUMB
AREA ||i.RCC_ADCCLKConfig||, CODE, READONLY, ALIGN=2
RCC_ADCCLKConfig PROC
;;;761 */
;;;762 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
000000 2100 MOVS r1,#0
;;;763 {
;;;764 uint32_t tmpreg = 0;
;;;765 /* Check the parameters */
;;;766 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
;;;767 tmpreg = RCC->CFGR;
000002 4a03 LDR r2,|L1.16|
000004 6851 LDR r1,[r2,#4]
;;;768 /* Clear ADCPRE[1:0] bits */
;;;769 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000006 f4214140 BIC r1,r1,#0xc000
;;;770 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
;;;771 tmpreg |= RCC_PCLK2;
00000a 4301 ORRS r1,r1,r0
;;;772 /* Store the new value */
;;;773 RCC->CFGR = tmpreg;
00000c 6051 STR r1,[r2,#4]
;;;774 }
00000e 4770 BX lr
;;;775
ENDP
|L1.16|
DCD 0x40021000
AREA ||i.RCC_AHBPeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_AHBPeriphClockCmd PROC
;;;1046 */
;;;1047 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
000000 b129 CBZ r1,|L2.14|
;;;1048 {
;;;1049 /* Check the parameters */
;;;1050 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;1051 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1052
;;;1053 if (NewState != DISABLE)
;;;1054 {
;;;1055 RCC->AHBENR |= RCC_AHBPeriph;
000002 4a06 LDR r2,|L2.28|
000004 6952 LDR r2,[r2,#0x14]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L2.28|
00000a 615a STR r2,[r3,#0x14]
00000c e004 B |L2.24|
|L2.14|
;;;1056 }
;;;1057 else
;;;1058 {
;;;1059 RCC->AHBENR &= ~RCC_AHBPeriph;
00000e 4a03 LDR r2,|L2.28|
000010 6952 LDR r2,[r2,#0x14]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L2.28|
000016 615a STR r2,[r3,#0x14]
|L2.24|
;;;1060 }
;;;1061 }
000018 4770 BX lr
;;;1062
ENDP
00001a 0000 DCW 0x0000
|L2.28|
DCD 0x40021000
AREA ||i.RCC_APB1PeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_APB1PeriphClockCmd PROC
;;;1105 */
;;;1106 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000 b129 CBZ r1,|L3.14|
;;;1107 {
;;;1108 /* Check the parameters */
;;;1109 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1110 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1111 if (NewState != DISABLE)
;;;1112 {
;;;1113 RCC->APB1ENR |= RCC_APB1Periph;
000002 4a06 LDR r2,|L3.28|
000004 69d2 LDR r2,[r2,#0x1c]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L3.28|
00000a 61da STR r2,[r3,#0x1c]
00000c e004 B |L3.24|
|L3.14|
;;;1114 }
;;;1115 else
;;;1116 {
;;;1117 RCC->APB1ENR &= ~RCC_APB1Periph;
00000e 4a03 LDR r2,|L3.28|
000010 69d2 LDR r2,[r2,#0x1c]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L3.28|
000016 61da STR r2,[r3,#0x1c]
|L3.24|
;;;1118 }
;;;1119 }
000018 4770 BX lr
;;;1120
ENDP
00001a 0000 DCW 0x0000
|L3.28|
DCD 0x40021000
AREA ||i.RCC_APB1PeriphResetCmd||, CODE, READONLY, ALIGN=2
RCC_APB1PeriphResetCmd PROC
;;;1192 */
;;;1193 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
000000 b129 CBZ r1,|L4.14|
;;;1194 {
;;;1195 /* Check the parameters */
;;;1196 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;1197 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1198 if (NewState != DISABLE)
;;;1199 {
;;;1200 RCC->APB1RSTR |= RCC_APB1Periph;
000002 4a06 LDR r2,|L4.28|
000004 6912 LDR r2,[r2,#0x10]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L4.28|
00000a 611a STR r2,[r3,#0x10]
00000c e004 B |L4.24|
|L4.14|
;;;1201 }
;;;1202 else
;;;1203 {
;;;1204 RCC->APB1RSTR &= ~RCC_APB1Periph;
00000e 4a03 LDR r2,|L4.28|
000010 6912 LDR r2,[r2,#0x10]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L4.28|
000016 611a STR r2,[r3,#0x10]
|L4.24|
;;;1205 }
;;;1206 }
000018 4770 BX lr
;;;1207
ENDP
00001a 0000 DCW 0x0000
|L4.28|
DCD 0x40021000
AREA ||i.RCC_APB2PeriphClockCmd||, CODE, READONLY, ALIGN=2
RCC_APB2PeriphClockCmd PROC
;;;1075 */
;;;1076 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000 b129 CBZ r1,|L5.14|
;;;1077 {
;;;1078 /* Check the parameters */
;;;1079 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1080 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1081 if (NewState != DISABLE)
;;;1082 {
;;;1083 RCC->APB2ENR |= RCC_APB2Periph;
000002 4a06 LDR r2,|L5.28|
000004 6992 LDR r2,[r2,#0x18]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L5.28|
00000a 619a STR r2,[r3,#0x18]
00000c e004 B |L5.24|
|L5.14|
;;;1084 }
;;;1085 else
;;;1086 {
;;;1087 RCC->APB2ENR &= ~RCC_APB2Periph;
00000e 4a03 LDR r2,|L5.28|
000010 6992 LDR r2,[r2,#0x18]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L5.28|
000016 619a STR r2,[r3,#0x18]
|L5.24|
;;;1088 }
;;;1089 }
000018 4770 BX lr
;;;1090
ENDP
00001a 0000 DCW 0x0000
|L5.28|
DCD 0x40021000
AREA ||i.RCC_APB2PeriphResetCmd||, CODE, READONLY, ALIGN=2
RCC_APB2PeriphResetCmd PROC
;;;1162 */
;;;1163 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
000000 b129 CBZ r1,|L6.14|
;;;1164 {
;;;1165 /* Check the parameters */
;;;1166 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;1167 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1168 if (NewState != DISABLE)
;;;1169 {
;;;1170 RCC->APB2RSTR |= RCC_APB2Periph;
000002 4a06 LDR r2,|L6.28|
000004 68d2 LDR r2,[r2,#0xc]
000006 4302 ORRS r2,r2,r0
000008 4b04 LDR r3,|L6.28|
00000a 60da STR r2,[r3,#0xc]
00000c e004 B |L6.24|
|L6.14|
;;;1171 }
;;;1172 else
;;;1173 {
;;;1174 RCC->APB2RSTR &= ~RCC_APB2Periph;
00000e 4a03 LDR r2,|L6.28|
000010 68d2 LDR r2,[r2,#0xc]
000012 4382 BICS r2,r2,r0
000014 4b01 LDR r3,|L6.28|
000016 60da STR r2,[r3,#0xc]
|L6.24|
;;;1175 }
;;;1176 }
000018 4770 BX lr
;;;1177
ENDP
00001a 0000 DCW 0x0000
|L6.28|
DCD 0x40021000
AREA ||i.RCC_AdjustHSICalibrationValue||, CODE, READONLY, ALIGN=2
RCC_AdjustHSICalibrationValue PROC
;;;333 */
;;;334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
000000 2100 MOVS r1,#0
;;;335 {
;;;336 uint32_t tmpreg = 0;
;;;337 /* Check the parameters */
;;;338 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
;;;339 tmpreg = RCC->CR;
000002 4a04 LDR r2,|L7.20|
000004 6811 LDR r1,[r2,#0]
;;;340 /* Clear HSITRIM[4:0] bits */
;;;341 tmpreg &= CR_HSITRIM_Mask;
000006 f02101f8 BIC r1,r1,#0xf8
;;;342 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
;;;343 tmpreg |= (uint32_t)HSICalibrationValue << 3;
00000a ea4101c0 ORR r1,r1,r0,LSL #3
;;;344 /* Store the new value */
;;;345 RCC->CR = tmpreg;
00000e 6011 STR r1,[r2,#0]
;;;346 }
000010 4770 BX lr
;;;347
ENDP
000012 0000 DCW 0x0000
|L7.20|
DCD 0x40021000
AREA ||i.RCC_BackupResetCmd||, CODE, READONLY, ALIGN=2
RCC_BackupResetCmd PROC
;;;1213 */
;;;1214 void RCC_BackupResetCmd(FunctionalState NewState)
000000 4901 LDR r1,|L8.8|
;;;1215 {
;;;1216 /* Check the parameters */
;;;1217 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1218 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
000002 6008 STR r0,[r1,#0]
;;;1219 }
000004 4770 BX lr
;;;1220
ENDP
000006 0000 DCW 0x0000
|L8.8|
DCD 0x42420440
AREA ||i.RCC_ClearFlag||, CODE, READONLY, ALIGN=2
RCC_ClearFlag PROC
;;;1347 */
;;;1348 void RCC_ClearFlag(void)
000000 4803 LDR r0,|L9.16|
;;;1349 {
;;;1350 /* Set RMVF bit to clear the reset flags */
;;;1351 RCC->CSR |= CSR_RMVF_Set;
000002 6a40 LDR r0,[r0,#0x24]
000004 f0407080 ORR r0,r0,#0x1000000
000008 4901 LDR r1,|L9.16|
00000a 6248 STR r0,[r1,#0x24]
;;;1352 }
00000c 4770 BX lr
;;;1353
ENDP
00000e 0000 DCW 0x0000
|L9.16|
DCD 0x40021000
AREA ||i.RCC_ClearITPendingBit||, CODE, READONLY, ALIGN=2
RCC_ClearITPendingBit PROC
;;;1424 */
;;;1425 void RCC_ClearITPendingBit(uint8_t RCC_IT)
000000 4901 LDR r1,|L10.8|
;;;1426 {
;;;1427 /* Check the parameters */
;;;1428 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
;;;1429
;;;1430 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
;;;1431 pending bits */
;;;1432 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
000002 7288 STRB r0,[r1,#0xa]
;;;1433 }
000004 4770 BX lr
;;;1434
ENDP
000006 0000 DCW 0x0000
|L10.8|
DCD 0x40021000
AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2
RCC_ClockSecuritySystemCmd PROC
;;;1226 */
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