?? stm32f10x_tim.txt
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; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_tim.o --depend=.\Obj\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O0 -Otime -I..\..\Libraries\CMSIS\Core\CM3 -I..\..\Libraries\STM32F10x_StdPeriph_Driver\inc -I..\..\Source\inc -Id:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB -DSTM32F10X_HD -DUSE_STDPERIPH_DRIVER ..\..\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c]
THUMB
AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=1
TI1_Config PROC
;;;2654 */
;;;2655 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000 b5f0 PUSH {r4-r7,lr}
;;;2656 uint16_t TIM_ICFilter)
;;;2657 {
;;;2658 uint16_t tmpccmr1 = 0, tmpccer = 0;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
;;;2659 /* Disable the Channel 1: Reset the CC1E Bit */
;;;2660 TIMx->CCER &= CCER_CC1E_Reset;
000006 8c06 LDRH r6,[r0,#0x20]
000008 f64f77fe MOV r7,#0xfffe
00000c 403e ANDS r6,r6,r7
00000e 8406 STRH r6,[r0,#0x20]
;;;2661 tmpccmr1 = TIMx->CCMR1;
000010 8b04 LDRH r4,[r0,#0x18]
;;;2662 tmpccer = TIMx->CCER;
000012 8c05 LDRH r5,[r0,#0x20]
;;;2663 /* Select the Input and set the filter */
;;;2664 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
000014 f64f760c MOV r6,#0xff0c
000018 4034 ANDS r4,r4,r6
;;;2665 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
00001a 051e LSLS r6,r3,#20
00001c ea424616 ORR r6,r2,r6,LSR #16
000020 4334 ORRS r4,r4,r6
;;;2666 /* Select the Polarity and set the CC1E Bit */
;;;2667 tmpccer &= CCER_CC1P_Reset;
000022 1e7e SUBS r6,r7,#1
000024 4035 ANDS r5,r5,r6
;;;2668 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)CCER_CC1E_Set);
000026 f0410601 ORR r6,r1,#1
00002a 4335 ORRS r5,r5,r6
;;;2669 /* Write to TIMx CCMR1 and CCER registers */
;;;2670 TIMx->CCMR1 = tmpccmr1;
00002c 8304 STRH r4,[r0,#0x18]
;;;2671 TIMx->CCER = tmpccer;
00002e 8405 STRH r5,[r0,#0x20]
;;;2672 }
000030 bdf0 POP {r4-r7,pc}
;;;2673
ENDP
AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1
TI2_Config PROC
;;;2689 */
;;;2690 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000 b5f0 PUSH {r4-r7,lr}
;;;2691 uint16_t TIM_ICFilter)
;;;2692 {
;;;2693 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
000006 2600 MOVS r6,#0
;;;2694 /* Disable the Channel 2: Reset the CC2E Bit */
;;;2695 TIMx->CCER &= CCER_CC2E_Reset;
000008 8c07 LDRH r7,[r0,#0x20]
00000a f64f7cef MOV r12,#0xffef
00000e ea07070c AND r7,r7,r12
000012 8407 STRH r7,[r0,#0x20]
;;;2696 tmpccmr1 = TIMx->CCMR1;
000014 8b04 LDRH r4,[r0,#0x18]
;;;2697 tmpccer = TIMx->CCER;
000016 8c05 LDRH r5,[r0,#0x20]
;;;2698 tmp = (uint16_t)(TIM_ICPolarity << 4);
000018 050f LSLS r7,r1,#20
00001a 0c3e LSRS r6,r7,#16
;;;2699 /* Select the Input and set the filter */
;;;2700 tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
00001c f64047ff MOV r7,#0xcff
000020 403c ANDS r4,r4,r7
;;;2701 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
000022 071f LSLS r7,r3,#28
000024 ea444417 ORR r4,r4,r7,LSR #16
;;;2702 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
000028 0617 LSLS r7,r2,#24
00002a ea444417 ORR r4,r4,r7,LSR #16
;;;2703 /* Select the Polarity and set the CC2E Bit */
;;;2704 tmpccer &= CCER_CC2P_Reset;
00002e f64f77df MOV r7,#0xffdf
000032 403d ANDS r5,r5,r7
;;;2705 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC2E_Set);
000034 f0460710 ORR r7,r6,#0x10
000038 433d ORRS r5,r5,r7
;;;2706 /* Write to TIMx CCMR1 and CCER registers */
;;;2707 TIMx->CCMR1 = tmpccmr1 ;
00003a 8304 STRH r4,[r0,#0x18]
;;;2708 TIMx->CCER = tmpccer;
00003c 8405 STRH r5,[r0,#0x20]
;;;2709 }
00003e bdf0 POP {r4-r7,pc}
;;;2710
ENDP
AREA ||i.TI3_Config||, CODE, READONLY, ALIGN=1
TI3_Config PROC
;;;2726 */
;;;2727 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000 b5f0 PUSH {r4-r7,lr}
;;;2728 uint16_t TIM_ICFilter)
;;;2729 {
;;;2730 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
000002 2500 MOVS r5,#0
000004 2400 MOVS r4,#0
000006 2600 MOVS r6,#0
;;;2731 /* Disable the Channel 3: Reset the CC3E Bit */
;;;2732 TIMx->CCER &= CCER_CC3E_Reset;
000008 8c07 LDRH r7,[r0,#0x20]
00000a f64f6cff MOV r12,#0xfeff
00000e ea07070c AND r7,r7,r12
000012 8407 STRH r7,[r0,#0x20]
;;;2733 tmpccmr2 = TIMx->CCMR2;
000014 8b85 LDRH r5,[r0,#0x1c]
;;;2734 tmpccer = TIMx->CCER;
000016 8c04 LDRH r4,[r0,#0x20]
;;;2735 tmp = (uint16_t)(TIM_ICPolarity << 8);
000018 060f LSLS r7,r1,#24
00001a 0c3e LSRS r6,r7,#16
;;;2736 /* Select the Input and set the filter */
;;;2737 tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
00001c f64f770c MOV r7,#0xff0c
000020 403d ANDS r5,r5,r7
;;;2738 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
000022 051f LSLS r7,r3,#20
000024 ea424717 ORR r7,r2,r7,LSR #16
000028 433d ORRS r5,r5,r7
;;;2739 /* Select the Polarity and set the CC3E Bit */
;;;2740 tmpccer &= CCER_CC3P_Reset;
00002a f64f57ff MOV r7,#0xfdff
00002e 403c ANDS r4,r4,r7
;;;2741 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC3E_Set);
000030 f4467780 ORR r7,r6,#0x100
000034 433c ORRS r4,r4,r7
;;;2742 /* Write to TIMx CCMR2 and CCER registers */
;;;2743 TIMx->CCMR2 = tmpccmr2;
000036 8385 STRH r5,[r0,#0x1c]
;;;2744 TIMx->CCER = tmpccer;
000038 8404 STRH r4,[r0,#0x20]
;;;2745 }
00003a bdf0 POP {r4-r7,pc}
;;;2746
ENDP
AREA ||i.TI4_Config||, CODE, READONLY, ALIGN=1
TI4_Config PROC
;;;2762 */
;;;2763 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
000000 b5f0 PUSH {r4-r7,lr}
;;;2764 uint16_t TIM_ICFilter)
;;;2765 {
;;;2766 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
000002 2400 MOVS r4,#0
000004 2500 MOVS r5,#0
000006 2600 MOVS r6,#0
;;;2767
;;;2768 /* Disable the Channel 4: Reset the CC4E Bit */
;;;2769 TIMx->CCER &= CCER_CC4E_Reset;
000008 8c07 LDRH r7,[r0,#0x20]
00000a f64e7cff MOV r12,#0xefff
00000e ea07070c AND r7,r7,r12
000012 8407 STRH r7,[r0,#0x20]
;;;2770 tmpccmr2 = TIMx->CCMR2;
000014 8b84 LDRH r4,[r0,#0x1c]
;;;2771 tmpccer = TIMx->CCER;
000016 8c05 LDRH r5,[r0,#0x20]
;;;2772 tmp = (uint16_t)(TIM_ICPolarity << 12);
000018 070f LSLS r7,r1,#28
00001a 0c3e LSRS r6,r7,#16
;;;2773
;;;2774 /* Select the Input and set the filter */
;;;2775 tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
00001c f64047ff MOV r7,#0xcff
000020 403c ANDS r4,r4,r7
;;;2776 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
000022 0617 LSLS r7,r2,#24
000024 ea444417 ORR r4,r4,r7,LSR #16
;;;2777 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
000028 071f LSLS r7,r3,#28
00002a ea444417 ORR r4,r4,r7,LSR #16
;;;2778
;;;2779 /* Select the Polarity and set the CC4E Bit */
;;;2780 tmpccer &= CCER_CC4P_Reset;
00002e f64d77ff MOV r7,#0xdfff
000032 403d ANDS r5,r5,r7
;;;2781 tmpccer |= (uint16_t)(tmp | (uint16_t)CCER_CC4E_Set);
000034 f4465780 ORR r7,r6,#0x1000
000038 433d ORRS r5,r5,r7
;;;2782 /* Write to TIMx CCMR2 and CCER registers */
;;;2783 TIMx->CCMR2 = tmpccmr2;
00003a 8384 STRH r4,[r0,#0x1c]
;;;2784 TIMx->CCER = tmpccer ;
00003c 8405 STRH r5,[r0,#0x20]
;;;2785 }
00003e bdf0 POP {r4-r7,pc}
;;;2786
ENDP
AREA ||i.TIM_ARRPreloadConfig||, CODE, READONLY, ALIGN=1
TIM_ARRPreloadConfig PROC
;;;1385 */
;;;1386 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000 b121 CBZ r1,|L5.12|
;;;1387 {
;;;1388 /* Check the parameters */
;;;1389 assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;1390 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1391 if (NewState != DISABLE)
;;;1392 {
;;;1393 /* Set the ARR Preload Bit */
;;;1394 TIMx->CR1 |= CR1_ARPE_Set;
000002 8802 LDRH r2,[r0,#0]
000004 f0420280 ORR r2,r2,#0x80
000008 8002 STRH r2,[r0,#0]
00000a e004 B |L5.22|
|L5.12|
;;;1395 }
;;;1396 else
;;;1397 {
;;;1398 /* Reset the ARR Preload Bit */
;;;1399 TIMx->CR1 &= CR1_ARPE_Reset;
00000c 8802 LDRH r2,[r0,#0]
00000e f240337f MOV r3,#0x37f
000012 401a ANDS r2,r2,r3
000014 8002 STRH r2,[r0,#0]
|L5.22|
;;;1400 }
;;;1401 }
000016 4770 BX lr
;;;1402
ENDP
AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1
TIM_BDTRConfig PROC
;;;693 */
;;;694 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
000000 880a LDRH r2,[r1,#0]
;;;695 {
;;;696 /* Check the parameters */
;;;697 assert_param(IS_TIM_18_PERIPH(TIMx));
;;;698 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;699 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;700 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;701 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;702 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;703 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;704 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
;;;705 the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;706 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
000002 884b LDRH r3,[r1,#2]
000004 431a ORRS r2,r2,r3
000006 888b LDRH r3,[r1,#4]
000008 431a ORRS r2,r2,r3
00000a 88cb LDRH r3,[r1,#6]
00000c 431a ORRS r2,r2,r3
00000e 890b LDRH r3,[r1,#8]
000010 431a ORRS r2,r2,r3
000012 894b LDRH r3,[r1,#0xa]
000014 431a ORRS r2,r2,r3
000016 898b LDRH r3,[r1,#0xc]
000018 431a ORRS r2,r2,r3
00001a f8a02044 STRH r2,[r0,#0x44]
;;;707 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;708 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;709 TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;710 }
00001e 4770 BX lr
;;;711
ENDP
AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1
TIM_BDTRStructInit PROC
;;;768 */
;;;769 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
000000 2100 MOVS r1,#0
;;;770 {
;;;771 /* Set the default configuration */
;;;772 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
000002 8001 STRH r1,[r0,#0]
;;;773 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
000004 8041 STRH r1,[r0,#2]
;;;774 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
000006 8081 STRH r1,[r0,#4]
;;;775 TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
000008 80c1 STRH r1,[r0,#6]
;;;776 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00000a 8101 STRH r1,[r0,#8]
;;;777 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00000c 8141 STRH r1,[r0,#0xa]
;;;778 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00000e 8181 STRH r1,[r0,#0xc]
;;;779 }
000010 4770 BX lr
;;;780
ENDP
AREA ||i.TIM_CCPreloadControl||, CODE, READONLY, ALIGN=1
TIM_CCPreloadControl PROC
;;;1457 */
;;;1458 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
000000 b121 CBZ r1,|L8.12|
;;;1459 {
;;;1460 /* Check the parameters */
;;;1461 assert_param(IS_TIM_18_PERIPH(TIMx));
;;;1462 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1463 if (NewState != DISABLE)
;;;1464 {
;;;1465 /* Set the CCPC Bit */
;;;1466 TIMx->CR2 |= CR2_CCPC_Set;
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