#define B0RAT_7			0x00000700	/* Bank 0 Read Access Time = 7 cycles */#define B0RAT_8			0x00000800	/* Bank 0 Read Access Time = 8 cycles */#define B0RAT_9			0x00000900	/* Bank 0 Read Access Time = 9 cycles */#define B0RAT_10		0x00000A00	/* Bank 0 Read Access Time = 10 cycles */#define B0RAT_11		0x00000B00	/* Bank 0 Read Access Time = 11 cycles */#define B0RAT_12		0x00000C00	/* Bank 0 Read Access Time = 12 cycles */#define B0RAT_13		0x00000D00	/* Bank 0 Read Access Time = 13 cycles */#define B0RAT_14		0x00000E00	/* Bank 0 Read Access Time = 14 cycles */#define B0RAT_15		0x00000F00	/* Bank 0 Read Access Time = 15 cycles */#define B0WAT_1			0x00001000	/* Bank 0 Write Access Time = 1 cycle */#define B0WAT_2			0x00002000	/* Bank 0 Write Access Time = 2 cycles */#define B0WAT_3			0x00003000	/* Bank 0 Write Access Time = 3 cycles */#define B0WAT_4			0x00004000	/* Bank 0 Write Access Time = 4 cycles */#define B0WAT_5			0x00005000	/* Bank 0 Write Access Time = 5 cycles */#define B0WAT_6			0x00006000	/* Bank 0 Write Access Time = 6 cycles */#define B0WAT_7			0x00007000	/* Bank 0 Write Access Time = 7 cycles */#define B0WAT_8			0x00008000	/* Bank 0 Write Access Time = 8 cycles */#define B0WAT_9			0x00009000	/* Bank 0 Write Access Time = 9 cycles */#define B0WAT_10		0x0000A000	/* Bank 0 Write Access Time = 10 cycles */#define B0WAT_11		0x0000B000	/* Bank 0 Write Access Time = 11 cycles */#define B0WAT_12		0x0000C000	/* Bank 0 Write Access Time = 12 cycles */#define B0WAT_13		0x0000D000	/* Bank 0 Write Access Time = 13 cycles */#define B0WAT_14		0x0000E000	/* Bank 0 Write Access Time = 14 cycles */#define B0WAT_15		0x0000F000	/* Bank 0 Write Access Time = 15 cycles */#define B1RDYEN			0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */#define B1RDYPOL		0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */#define B1TT_1			0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */#define B1TT_2			0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */#define B1TT_3			0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */#define B1TT_4			0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */#define B1ST_1			0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B1ST_2			0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B1ST_3			0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B1ST_4			0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B1HT_1			0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B1HT_2			0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B1HT_3			0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B1HT_0			0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B1RAT_1			0x01000000	/* Bank 1 Read Access Time = 1 cycle */#define B1RAT_2			0x02000000	/* Bank 1 Read Access Time = 2 cycles */#define B1RAT_3			0x03000000	/* Bank 1 Read Access Time = 3 cycles */#define B1RAT_4			0x04000000	/* Bank 1 Read Access Time = 4 cycles */#define B1RAT_5			0x05000000	/* Bank 1 Read Access Time = 5 cycles */#define B1RAT_6			0x06000000	/* Bank 1 Read Access Time = 6 cycles */#define B1RAT_7			0x07000000	/* Bank 1 Read Access Time = 7 cycles */#define B1RAT_8			0x08000000	/* Bank 1 Read Access Time = 8 cycles */#define B1RAT_9			0x09000000	/* Bank 1 Read Access Time = 9 cycles */#define B1RAT_10		0x0A000000	/* Bank 1 Read Access Time = 10 cycles */#define B1RAT_11		0x0B000000	/* Bank 1 Read Access Time = 11 cycles */#define B1RAT_12		0x0C000000	/* Bank 1 Read Access Time = 12 cycles */#define B1RAT_13		0x0D000000	/* Bank 1 Read Access Time = 13 cycles */#define B1RAT_14		0x0E000000	/* Bank 1 Read Access Time = 14 cycles */#define B1RAT_15		0x0F000000	/* Bank 1 Read Access Time = 15 cycles */#define B1WAT_1			0x10000000	/* Bank 1 Write Access Time = 1 cycle */#define B1WAT_2			0x20000000	/* Bank 1 Write Access Time = 2 cycles */#define B1WAT_3			0x30000000	/* Bank 1 Write Access Time = 3 cycles */#define B1WAT_4			0x40000000	/* Bank 1 Write Access Time = 4 cycles */#define B1WAT_5			0x50000000	/* Bank 1 Write Access Time = 5 cycles */#define B1WAT_6			0x60000000	/* Bank 1 Write Access Time = 6 cycles */#define B1WAT_7			0x70000000	/* Bank 1 Write Access Time = 7 cycles */#define B1WAT_8			0x80000000	/* Bank 1 Write Access Time = 8 cycles */#define B1WAT_9			0x90000000	/* Bank 1 Write Access Time = 9 cycles */#define B1WAT_10		0xA0000000	/* Bank 1 Write Access Time = 10 cycles */#define B1WAT_11		0xB0000000	/* Bank 1 Write Access Time = 11 cycles */#define B1WAT_12		0xC0000000	/* Bank 1 Write Access Time = 12 cycles */#define B1WAT_13		0xD0000000	/* Bank 1 Write Access Time = 13 cycles */#define B1WAT_14		0xE0000000	/* Bank 1 Write Access Time = 14 cycles */#define B1WAT_15		0xF0000000	/* Bank 1 Write Access Time = 15 cycles *//* AMBCTL1 Masks */#define B2RDYEN			0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */#define B2RDYPOL		0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */#define B2TT_1			0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */#define B2TT_2			0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */#define B2TT_3			0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */#define B2TT_4			0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */#define B2ST_1			0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B2ST_2			0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B2ST_3			0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B2ST_4			0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B2HT_1			0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B2HT_2			0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B2HT_3			0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B2HT_0			0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B2RAT_1			0x00000100	/* Bank 2 Read Access Time = 1 cycle */#define B2RAT_2			0x00000200	/* Bank 2 Read Access Time = 2 cycles */#define B2RAT_3			0x00000300	/* Bank 2 Read Access Time = 3 cycles */#define B2RAT_4			0x00000400	/* Bank 2 Read Access Time = 4 cycles */#define B2RAT_5			0x00000500	/* Bank 2 Read Access Time = 5 cycles */#define B2RAT_6			0x00000600	/* Bank 2 Read Access Time = 6 cycles */#define B2RAT_7			0x00000700	/* Bank 2 Read Access Time = 7 cycles */#define B2RAT_8			0x00000800	/* Bank 2 Read Access Time = 8 cycles */#define B2RAT_9			0x00000900	/* Bank 2 Read Access Time = 9 cycles */#define B2RAT_10		0x00000A00	/* Bank 2 Read Access Time = 10 cycles */#define B2RAT_11		0x00000B00	/* Bank 2 Read Access Time = 11 cycles */#define B2RAT_12		0x00000C00	/* Bank 2 Read Access Time = 12 cycles */#define B2RAT_13		0x00000D00	/* Bank 2 Read Access Time = 13 cycles */#define B2RAT_14		0x00000E00	/* Bank 2 Read Access Time = 14 cycles */#define B2RAT_15		0x00000F00	/* Bank 2 Read Access Time = 15 cycles */#define B2WAT_1			0x00001000	/* Bank 2 Write Access Time = 1 cycle */#define B2WAT_2			0x00002000	/* Bank 2 Write Access Time = 2 cycles */#define B2WAT_3			0x00003000	/* Bank 2 Write Access Time = 3 cycles */#define B2WAT_4			0x00004000	/* Bank 2 Write Access Time = 4 cycles */#define B2WAT_5			0x00005000	/* Bank 2 Write Access Time = 5 cycles */#define B2WAT_6			0x00006000	/* Bank 2 Write Access Time = 6 cycles */#define B2WAT_7			0x00007000	/* Bank 2 Write Access Time = 7 cycles */#define B2WAT_8			0x00008000	/* Bank 2 Write Access Time = 8 cycles */#define B2WAT_9			0x00009000	/* Bank 2 Write Access Time = 9 cycles */#define B2WAT_10		0x0000A000	/* Bank 2 Write Access Time = 10 cycles */#define B2WAT_11		0x0000B000	/* Bank 2 Write Access Time = 11 cycles */#define B2WAT_12		0x0000C000	/* Bank 2 Write Access Time = 12 cycles */#define B2WAT_13		0x0000D000	/* Bank 2 Write Access Time = 13 cycles */#define B2WAT_14		0x0000E000	/* Bank 2 Write Access Time = 14 cycles */#define B2WAT_15		0x0000F000	/* Bank 2 Write Access Time = 15 cycles */#define B3RDYEN			0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */#define B3RDYPOL		0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */#define B3TT_1			0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */#define B3TT_2			0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */#define B3TT_3			0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */#define B3TT_4			0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */#define B3ST_1			0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B3ST_2			0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B3ST_3			0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B3ST_4			0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B3HT_1			0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B3HT_2			0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B3HT_3			0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B3HT_0			0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B3RAT_1			0x01000000	/* Bank 3 Read Access Time = 1 cycle */#define B3RAT_2			0x02000000	/* Bank 3 Read Access Time = 2 cycles */#define B3RAT_3			0x03000000	/* Bank 3 Read Access Time = 3 cycles */#define B3RAT_4			0x04000000	/* Bank 3 Read Access Time = 4 cycles */#define B3RAT_5			0x05000000	/* Bank 3 Read Access Time = 5 cycles */#define B3RAT_6			0x06000000	/* Bank 3 Read Access Time = 6 cycles */#define B3RAT_7			0x07000000	/* Bank 3 Read Access Time = 7 cycles */#define B3RAT_8			0x08000000	/* Bank 3 Read Access Time = 8 cycles */#define B3RAT_9			0x09000000	/* Bank 3 Read Access Time = 9 cycles */#define B3RAT_10		0x0A000000	/* Bank 3 Read Access Time = 10 cycles */#define B3RAT_11		0x0B000000	/* Bank 3 Read Access Time = 11 cycles */#define B3RAT_12		0x0C000000	/* Bank 3 Read Access Time = 12 cycles */#define B3RAT_13		0x0D000000	/* Bank 3 Read Access Time = 13 cycles */#define B3RAT_14		0x0E000000	/* Bank 3 Read Access Time = 14 cycles */#define B3RAT_15		0x0F000000	/* Bank 3 Read Access Time = 15 cycles */#define B3WAT_1			0x10000000	/* Bank 3 Write Access Time = 1 cycle */#define B3WAT_2			0x20000000	/* Bank 3 Write Access Time = 2 cycles */#define B3WAT_3			0x30000000	/* Bank 3 Write Access Time = 3 cycles */#define B3WAT_4			0x40000000	/* Bank 3 Write Access Time = 4 cycles */#define B3WAT_5			0x50000000	/* Bank 3 Write Access Time = 5 cycles */#define B3WAT_6			0x60000000	/* Bank 3 Write Access Time = 6 cycles */#define B3WAT_7			0x70000000	/* Bank 3 Write Access Time = 7 cycles */#define B3WAT_8			0x80000000	/* Bank 3 Write Access Time = 8 cycles */#define B3WAT_9			0x90000000	/* Bank 3 Write Access Time = 9 cycles */#define B3WAT_10		0xA0000000	/* Bank 3 Write Access Time = 10 cycles */#define B3WAT_11		0xB0000000	/* Bank 3 Write Access Time = 11 cycles */#define B3WAT_12		0xC0000000	/* Bank 3 Write Access Time = 12 cycles */#define B3WAT_13		0xD0000000	/* Bank 3 Write Access Time = 13 cycles */#define B3WAT_14		0xE0000000	/* Bank 3 Write Access Time = 14 cycles */#define B3WAT_15		0xF0000000	/* Bank 3 Write Access Time = 15 cycles *//* * SDRAM CONTROLLER MASKS *//* SDGCTL Masks */#define SCTLE			0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */#define CL_2			0x00000008	/* SDRAM CAS latency = 2 cycles */#define CL_3			0x0000000C	/* SDRAM CAS latency = 3 cycles */#define PFE			0x00000010	/* Enable SDRAM prefetch */#define PFP			0x00000020	/* Prefetch has priority over AMC requests */#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle */#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles */#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles */#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles */#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles */#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles */#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles */#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles */#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles */#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles */#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles */#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles */#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles */#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles */#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles */#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle */#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles */#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles */#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles */#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles */#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles */#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles */#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle */#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles */#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles */#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles */#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles */#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles */#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles */#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle */#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles */#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles */#define PUPSD			0x00200000	/* Power-up start delay */#define PSM			0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */#define PSS			0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */#define SRFS			0x01000000	/* Start SDRAM self-refresh mode */#define EBUFE			0x02000000	/* Enable external buffering timing */#define FBBRW			0x04000000	/* Fast back-to-back read write enable */#define EMREN			0x10000000	/* Extended mode register enable */#define TCSR			0x20000000	/* Temp compensated self refresh value 85 deg C */#define CDDBG			0x40000000	/* Tristate SDRAM controls during bus grant *//* EBIU_SDBCTL Masks */#define EBE			0x00000001	/* Enable SDRAM external bank */#define EBSZ_16			0x00000000	/* SDRAM external bank size = 16MB */#define EBSZ_32			0x00000002	/* SDRAM external bank size = 32MB */#define EBSZ_64			0x00000004	/* SDRAM external bank size = 64MB */#define EBSZ_128		0x00000006	/* SDRAM external bank size = 128MB */#define EBCAW_8			0x00000000	/* SDRAM external bank column address width = 8 bits */#define EBCAW_9			0x00000010	/* SDRAM external bank column address width = 9 bits */#define EBCAW_10		0x00000020	/* SDRAM external bank column address width = 9 bits */#define EBCAW_11		0x00000030	/* SDRAM external bank column address width = 9 bits *//* EBIU_SDSTAT Masks */#define SDCI			0x00000001	/* SDRAM controller is idle */#define SDSRA			0x00000002	/* SDRAM SDRAM self refresh is active */#define SDPUA			0x00000004	/* SDRAM power up active */#define SDRS			0x00000008	/* SDRAM is in reset state */#define SDEASE			0x00000010	/* SDRAM EAB sticky error status - W1C */#define BGSTAT			0x00000020	/* Bus granted */#endif /* _DEF_BF532_H */