?? s3c2440.s
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;// <o2.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o2.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o2.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 1 Control Register (BANKCON1)
;// <o3.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o3.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o3.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o3.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 2 Control Register (BANKCON2)
;// <o4.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o4.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o4.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o4.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 3 Control Register (BANKCON3)
;// <o5.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o5.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o5.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o5.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 4 Control Register (BANKCON4)
;// <o6.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o6.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o6.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o6.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 5 Control Register (BANKCON5)
;// <o7.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o7.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o7.2..3> Tacp: Page Mode Access Cycle at Page Mode
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o7.0..1> PMC: Page Mode Configuration
;// <0=> normal (1 data) <1=> 4 data <2=> 8 data <3=> 16 data
;// </h>
;// <h> Bank 6 Control Register (BANKCON6)
;// <o8.15..16> Memory Type Selection
;// <0=> ROM or SRAM <3=> SDRAM
;// <o8.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o8.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o8.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
;// <i> if type is SDRAM then parameter is Trcd
;// <i> For SDRAM 6 cycles setting is not allowed
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o8.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
;// <i> if type is SDRAM then parameter is SCAN
;// </h>
;// <h> Bank 7 Control Register (BANKCON7)
;// <o9.15..16> Memory Type Selection
;// <0=> ROM or SRAM <3=> SDRAM
;// <o9.13..14> Tacs: Address Set-up Time before nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.11..12> Tcos: Chip Selection Set-up Time before nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.8..10> Tacc: Access Cycle
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks <3=> 4 clocks
;// <4=> 6 clocks <5=> 8 clocks <6=> 10 clocks <7=> 14 clocks
;// <o9.6..7> Tcoh: Chip Selection Hold Time after nOE
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.4..5> Tcah: Address Hold Time after nGCS
;// <0=> 0 clocks <1=> 1 clocks <2=> 2 clocks <3=> 4 clocks
;// <o9.2..3> Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is Tacp,
;// <i> if type is SDRAM then parameter is Trcd
;// <i> For SDRAM 6 cycles setting is not allowed
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> 6 clocks
;// <o9.0..1> PMC/SCAN: Page Mode Configuration / Column Address Number <0-3>
;// <i> Parameter depends on Memory Type: if type SRAM then parameter is PMC,
;// <i> if type is SDRAM then parameter is SCAN
;// </h>
;// <h> SDRAM Refresh Control Register (REFRESH)
;// <o10.23> REFEN: SDRAM Refresh Enable
;// <o10.22> TREFMD: SDRAM Refresh Mode
;// <0=> CBR/Auto Refresh <1=> Self Refresh
;// <o10.20..21> Trp: SDRAM RAS Pre-charge Time
;// <0=> 2 clocks <1=> 3 clocks <2=> 4 clocks <3=> Reserved
;// <o10.18..19> Tsrc: SDRAM Semi Row Cycle Time
;// <i> SDRAM Row cycle time: Trc = Tsrc + Trp
;// <0=> 4 clocks <1=> 5 clocks <2=> 6 clocks <3=> 7 clocks
;// <o10.0..10> Refresh Counter <0-1023>
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
;// </h>
;// <h> Flexible Bank Size Register (BANKSIZE)
;// <o11.7> BURST_EN: ARM Core Burst Operation Enable
;// <o11.5> SCKE_EN: SDRAM Power Down Mode Enable
;// <o11.4> SCLK_EN: SCLK Enabled During SDRAM Access Cycle
;// <0=> SCLK is always active <1=> SCLK is active only during the access
;// <o11.0..2> BK76MAP: BANK6 and BANK7 Memory Map
;// <0=> 32MB / 32MB <1=> 64MB / 64MB <2=> 128MB / 128MB
;// <4=> 2MB / 2MB <5=> 4MB / 4MB <6=> 8MB / 8MB <7=> 16MB / 16MB
;// <o11.0..10> Refresh Counter <0-1023>
;// <i> Refresh Period = (2048 - Refresh Count + 1) / HCLK
;// </h>
;// <h> SDRAM Mode Register Set Register 6 (MRSRB6)
;// <o12.7> WBL: Write Burst Length
;// <0=> Burst (Fixed)
;// <o12.7..8> TM: Test Mode
;// <0=> Mode register set (Fixed)
;// <o12.4..6> CL: CAS Latency
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
;// <o12.3> BT: Burst Type
;// <0=> Sequential (Fixed)
;// <o12.0..2> BL: Burst Length
;// <0=> 1 (Fixed)
;// </h>
;// <h> SDRAM Mode Register Set Register 7 (MRSRB7)
;// <o13.7> WBL: Write Burst Length
;// <0=> Burst (Fixed)
;// <o13.7..8> TM: Test Mode
;// <0=> Mode register set (Fixed)
;// <o13.4..6> CL: CAS Latency
;// <0=> 1 clocks <1=> 2 clocks <2=> 3 clocks
;// <o13.3> BT: Burst Type
;// <0=> Sequential (Fixed)
;// <o13.0..2> BL: Burst Length
;// <0=> 1 (Fixed)
;// </h>
;// </e> Memory Controller Setup
MC_SETUP EQU 0
BWSCON_Val EQU 0x22000000
BANKCON0_Val EQU 0x00000700
BANKCON1_Val EQU 0x00000700
BANKCON2_Val EQU 0x00000700
BANKCON3_Val EQU 0x00000700
BANKCON4_Val EQU 0x00000700
BANKCON5_Val EQU 0x00000700
BANKCON6_Val EQU 0x00018005
BANKCON7_Val EQU 0x00018005
REFRESH_Val EQU 0x008404F3
BANKSIZE_Val EQU 0x00000032
MRSRB6_Val EQU 0x00000020
MRSRB7_Val EQU 0x00000020
;----------------------- I/O Port Definitions ----------------------------------
GPA_BASE EQU 0x56000000 ; GPA Base Address
GPB_BASE EQU 0x56000010 ; GPB Base Address
GPC_BASE EQU 0x56000020 ; GPC Base Address
GPD_BASE EQU 0x56000030 ; GPD Base Address
GPE_BASE EQU 0x56000040 ; GPE Base Address
GPF_BASE EQU 0x56000050 ; GPF Base Address
GPG_BASE EQU 0x56000060 ; GPG Base Address
GPH_BASE EQU 0x56000070 ; GPH Base Address
GPJ_BASE EQU 0x560000D0 ; GPJ Base Address
GPCON_OFS EQU 0x00 ; Control Register Offset
GPDAT_OFS EQU 0x04 ; Data Register Offset
GPUP_OFS EQU 0x08 ; Pull-up Disable Register Offset
;// <e> I/O Setup
GP_SETUP EQU 0
;// <e> Port A Settings
;// <h> Port A Control Register (GPACON)
;// <o1.22> GPA22 <0=> Output <1=> nFCE
;// <o1.21> GPA21 <0=> Output <1=> nRSTOUT
;// <o1.20> GPA20 <0=> Output <1=> nFRE
;// <o1.19> GPA19 <0=> Output <1=> nFWE
;// <o1.18> GPA18 <0=> Output <1=> ALE
;// <o1.17> GPA17 <0=> Output <1=> CLE
;// <o1.16> GPA16 <0=> Output <1=> nGCS[5]
;// <o1.15> GPA15 <0=> Output <1=> nGCS[4]
;// <o1.14> GPA14 <0=> Output <1=> nGCS[3]
;// <o1.13> GPA13 <0=> Output <1=> nGCS[2]
;// <o1.12> GPA12 <0=> Output <1=> nGCS[1]
;// <o1.11> GPA11 <0=> Output <1=> ADDR26
;// <o1.10> GPA10 <0=> Output <1=> ADDR25
;// <o1.9> GPA9 <0=> Output <1=> ADDR24
;// <o1.8> GPA8 <0=> Output <1=> ADDR23
;// <o1.7> GPA7 <0=> Output <1=> ADDR22
;// <o1.6> GPA6 <0=> Output <1=> ADDR21
;// <o1.5> GPA5 <0=> Output <1=> ADDR20
;// <o1.4> GPA4 <0=> Output <1=> ADDR19
;// <o1.3> GPA3 <0=> Output <1=> ADDR18
;// <o1.2> GPA2 <0=> Output <1=> ADDR17
;// <o1.1> GPA1 <0=> Output <1=> ADDR16
;// <o1.0> GPA0 <0=> Output <1=> ADDR0
;// </h>
;// </e>
GPA_SETUP EQU 0
GPACON_Val EQU 0x000003FF
;// <e> Port B Settings
;// <h> Port B Control Register (GPBCON)
;// <o1.20..21> GPB10 <0=> Input <1=> Output <2=> nXDREQ0 <3=> Reserved
;// <o1.18..19> GPB9 <0=> Input <1=> Output <2=> nXDACK0 <3=> Reserved
;// <o1.16..17> GPB8 <0=> Input <1=> Output <2=> nXDREQ1 <3=> Reserved
;// <o1.14..15> GPB7 <0=> Input <1=> Output <2=> nXDACK1 <3=> Reserved
;// <o1.12..13> GPB6 <0=> Input <1=> Output <2=> nXBREQ <3=> Reserved
;// <o1.10..11> GPB5 <0=> Input <1=> Output <2=> nXBACK <3=> Reserved
;// <o1.8..9> GPB4 <0=> Input <1=> Output <2=> TCLK[0] <3=> Reserved
;// <o1.6..7> GPB3 <0=> Input <1=> Output <2=> TOUT3 <3=> Reserved
;// <o1.4..5> GPB2 <0=> Input <1=> Output <2=> TOUT2 <3=> Reserved
;// <o1.2..3> GPB1 <0=> Input <1=> Output <2=> TOUT1 <3=> Reserved
;// <o1.0..1> GPB0 <0=> Input <1=> Output <2=> TOUT0 <3=> Reserved
;// </h>
;// <h> Port B Pull-up Settings Register (GPBUP)
;// <o2.10> GPB10 Pull-up Disable
;// <o2.9> GPB9 Pull-up Disable
;// <o2.8> GPB8 Pull-up Disable
;// <o2.7> GPB7 Pull-up Disable
;// <o2.6> GPB6 Pull-up Disable
;// <o2.5> GPB5 Pull-up Disable
;// <o2.4> GPB4 Pull-up Disable
;// <o2.3> GPB3 Pull-up Disable
;// <o2.2> GPB2 Pull-up Disable
;// <o2.1> GPB1 Pull-up Disable
;// <o2.0> GPB0 Pull-up Disable
;// </h>
;// </e>
GPB_SETUP EQU 0
GPBCON_Val EQU 0x00000000
GPBUP_Val EQU 0x00000000
;// <e> Port C Settings
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