Analysis & Synthesis report for ad0804
Wed Oct 15 17:55:10 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. State Machine - |ad0804|CS
  9. State Machine - |ad0804|NS
 10. State Machine - |ad0804|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|state
 11. Registers Removed During Synthesis
 12. Registers Protected by Synthesis
 13. Removed Registers Triggering Further Register Optimizations
 14. General Register Statistics
 15. Inverted Register Statistics
 16. Multiplexer Restructuring Statistics (Restructuring Performed)
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity
 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated
 20. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_c7p3:auto_generated|altsyncram_ogq1:altsyncram1
 21. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 22. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 23. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 24. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 25. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 26. Source assignments for sld_hub:sld_hub_inst
 27. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 28. Parameter Settings for User Entity Instance: Top-level Entity: |ad0804
 29. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 30. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 31. SignalTap II Logic Analyzer Settings
 32. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Wed Oct 15 17:55:10 2008    ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                      ; ad0804                                   ;
; Top-level Entity Name              ; ad0804                                   ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 550                                      ;
;     Total combinational functions  ; 425                                      ;