Fitter report for ram
Sat Aug 23 14:02:22 2008
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Control Signals
 15. Global & Other Fast Signals
 16. Non-Global High Fan-Out Signals
 17. Fitter RAM Summary
 18. Interconnect Usage Summary
 19. Fitter Device Options
 20. Operating Settings and Conditions
 21. Advanced Data - General
 22. Advanced Data - Placement Preparation
 23. Advanced Data - Placement
 24. Advanced Data - Routing
 25. Fitter Messages
 26. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Sat Aug 23 14:02:22 2008         ;
; Quartus II Version                 ; 7.2 Build 175 11/20/2007 SP 1 SJ Full Version ;
; Revision Name                      ; ram                                           ;
; Top-level Entity Name              ; ram                                           ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C8Q208C8                                   ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 0 / 8,256 ( 0 % )                             ;
;     Total combinational functions  ; 0 / 8,256 ( 0 % )                             ;
;     Dedicated logic registers      ; 0 / 8,256 ( 0 % )                             ;
; Total registers                    ; 0                                             ;
; Total pins                         ; 35 / 138 ( 25 % )                             ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 2,048 / 165,888 ( 1 % )                       ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % )                                ;
; Total PLLs                         ; 0 / 2 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C8Q208C8                    ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;