---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\usbsoftlock_TB.vhd
-- Create Time : 2004-4-20, 11:32
-- Title       : Test Bench for usbsoftlock
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua (louxinghua99@mails.tsinghua.edu.cn)
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
-- Version     : 1.0
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for usbsoftlock_tb
--
---------------------------------------------------------------------------------------------------

library ieee;
use work.pdiusbd12_package.all;
use work.usb_package.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity usbsoftlock_tb is
end usbsoftlock_tb;

architecture TB_ARCHITECTURE of usbsoftlock_tb is
	-- Component declaration of the tested unit
	component USBSoftLock is
	port(
		reset_n : in STD_LOGIC;
		clk : in STD_LOGIC;
		int_n_in : in STD_LOGIC;
		a0 : out STD_LOGIC;	 
		data : inout STD_LOGIC_VECTOR(7 downto 0);
		wr_n : out STD_LOGIC;
		rd_n : out STD_LOGIC;
		ale : out STD_LOGIC;
		cs_n : out STD_LOGIC;
		suspend: inout STD_LOGIC;
		d12_reset_n : out STD_LOGIC; 
		step : out std_logic_vector(7 downto 0);
		d12_wr : out STD_LOGIC;
		d12_rd : out STD_LOGIC 	
	); 
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal reset_n : std_logic := '0';
	signal clk : std_logic := '0';
	signal int_n_in : std_logic := '1';
	signal data : std_logic_vector(7 downto 0);
	signal write : std_logic := '1';
	-- Observed signals - signals mapped to the output ports of tested entity
	signal a0 : std_logic := '0';
	signal wr_n : std_logic := '1';
	signal rd_n : std_logic := '1';
	signal	ale : STD_LOGIC := '1';
	signal	cs_n : STD_LOGIC := '1';
	signal	suspend: STD_LOGIC := '1';
	signal	d12_reset_n:  STD_LOGIC := '1';
	signal step : STD_LOGIC_VECTOR(7 downto 0) := X"FF";	
	
	signal d12_wr, d12_rd : STD_LOGIC := '1';
	
	-- for test
	signal td : REG256x8 :=
	(
	-- 1. get descriptor (1st time) test data
	X"01", X"00", X"20", X"00", X"08",  						   	-- [IR0][IR1][LTS][BUF0][BUF_LENGTH] 
	X"80", X"06", X"00", X"01", X"00", X"00", X"40", X"00",		   	-- setup packet: get descriptor
	X"00",															-- read data before writing endpoint0		
	
	-- 2. set address test data		   
	X"01", X"00", X"20", X"00", X"08", 								-- [IR0][IR1][LTS][BUF0][BUF_LENGTH]
	X"00", X"05", X"02", X"00", X"00", X"00", X"00", X"00", 		-- setup packet: set address
	X"00",														   	-- read data before writing endpoint0
	
	-- 3. get descriptor test data
	X"01", X"00", X"20", X"00", X"08",  						   	-- [IR0][IR1][LTS][BUF0][BUF_LENGTH] 
	X"80", X"06", X"00", X"01", X"00", X"00", X"12", X"00",		   	-- setup packet: get descriptor
	X"00",
	X"02", X"00", X"00", X"00",										-- [IR0][IR1][LTS][read data before writing endpoint0] 
	
	-- 4. get configuration test data
	X"01",	X"00", X"20", X"00", X"08",  						   	-- [IR0][IR1][LTS][BUF0][BUF_LENGTH] 
	X"80", X"06", X"00", X"02", X"00", X"00", X"09", X"00",		   	-- setup packet: get descriptor(configuration)
	X"00",
	
	-- 5. get configuration(all) test data
	X"01",	X"00", X"20", X"00", X"08",  						   	-- [IR0][IR1][LTS][BUF0][BUF_LENGTH] 
	X"80", X"06", X"00", X"02", X"00", X"00", X"FF", X"00",		   	-- setup packet: get descriptor(configuration)
	X"00",									   
	X"02", X"00", X"00", X"00",										-- [IR0][IR1][LTS][read data before writing endpoint0] 
	X"02", X"00", X"00", X"00",										-- [IR0][IR1][LTS][read data before writing endpoint0] 

	-- 6. set configuration
	X"01", X"00", X"20", X"00", X"08", 								-- [IR0][IR1][LTS][BUF0][BUF_LENGTH]
	X"00", X"09", X"01", X"00", X"00", X"00", X"00", X"00", 		-- setup packet: set address
	X"00",															-- read data before writing endpoint0		
	
	others => X"00"
	);	
	signal td_index : INTEGER8 := 255;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : usbsoftlock
		port map (
			reset_n => reset_n,
			clk => clk,
			int_n_in => int_n_in,
			a0 => a0,
			ale => ale,
			d12_reset_n => d12_reset_n,
			suspend => suspend,
			cs_n => cs_n,
			data => data,
			wr_n => wr_n,
			rd_n => rd_n,			   
			step => step,
			d12_wr => d12_wr,
			d12_rd => d12_rd
		);

	-- Add your stimulus here ... 	
	-- clock generate process
	clk_gen: process		
	begin
		clk <= not clk;
		wait for 50 ns;
	end process;
	
	-- main process
	main: process 
	variable i : INTEGER8;
	begin 
		-- 0 <-> 1ms, test reset and clock generate	
		reset_n <= '0';
		wait for 100 ns;
		reset_n <= '1';
		wait for 100 us; 
		
		for i in 0 to 10 loop
			int_n_in <= '0';
			wait for 3200 ns;
			int_n_in <= '1';
			wait for 300 us;
		end loop;	
		
		wait;
		
	end process;  		 
	
	-- read data process
	read_data: process(rd_n)		   
	begin
		if falling_edge(rd_n) then 
			if td_index = 255 then
				td_index <= 0;
			else
				td_index <= td_index+1;
			end if;
		end if;
	end process;
	
	process(d12_wr, td_index)
	begin
		if d12_wr = '0' then
			data <= "ZZZZZZZZ";
		else				   
			data <= td(td_index);
		end if;
	end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_usbsoftlock of usbsoftlock_tb is
	for TB_ARCHITECTURE
		for UUT : usbsoftlock
			use entity work.usbsoftlock(usbsoftlock);
		end for;
	end for;
end TESTBENCH_FOR_usbsoftlock;