---------------------------------------------------------------------------------------------------
--
-- Title       : EdgeController
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua (louxinghua99@mails.tsinghua.edu.cn)
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
--
---------------------------------------------------------------------------------------------------
--
-- File        : e:\Courses\ComputerHardwareInterface\USB_IF_DESIGN\USB_IF\src\EdgeController.vhd
-- Generated   : Fri Apr 16 19:23:36 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
-- This Module can generate an edge signal by the combination of input signals
-- Written by Lou Xinghua
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {EdgeController} architecture {EdgeController}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity EdgeController is
	port(
		clk : in STD_LOGIC;	
		ce_n : in STD_LOGIC;	  
		edge : out STD_LOGIC
	);
end EdgeController;

--}} End of automatically maintained section

architecture EdgeController of EdgeController is
begin

	-- enter your statements here -- 
	
	-- signal connection  
	edge <= clk when ce_n = '0' else
			'1';

end EdgeController;