?? pdiusbd12_package.vhd

?? fpga介紹及其相關(guān)實驗代碼等等,fpga介紹及其相關(guān)實驗代碼
?? VHD
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---------------------------------------------------------------------------------------------------
--
-- File        : PDIUSBD12_PACKAGE.vhd
-- Create Time : Fri Apr 16 20:39:30 2004
-- Title       : PDIUSBD12_PACKAGE
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua (louxinghua99@mails.tsinghua.edu.cn)
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
-- Version     : 1.0
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
-- USB Package, where device detail information included.
-- Written by Lou Xinghua	
--
---------------------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use WORK.USB_PACKAGE.all;



package PDIUSBD12_PACKAGE is	   

---------------------------------------------------------------------------------------------------
-- State Machine
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
-- PDIUSBD12 Device Constant
---------------------------------------------------------------------------------------------------

-- Constant
constant CLOCK_DIV_FACTOR: INTEGER8 := 15;	  
constant PULSE_WIDTH_FACTOR: INTEGER8 := 32; 
constant RESET_D12_DELAY: INTEGER range 0 to 10000 := 3;

-- A0 Values
constant D12_COMMAND: STD_LOGIC := '1';
constant D12_DATA: STD_LOGIC := '0';

-- D12 Command														  
constant D12_COMMAND_ENABLE_ADDRESS: STD_LOGIC_VECTOR(7 downto 0) := X"D0"; 
constant D12_COMMAND_ENABLE_ENDPOINT: STD_LOGIC_VECTOR(7 downto 0) := X"D8";
constant D12_COMMAND_SET_MODE: STD_LOGIC_VECTOR(7 downto 0) := X"F3";
constant D12_COMMAND_SET_DMA: STD_LOGIC_VECTOR(7 downto 0) := X"FB";
constant D12_COMMAND_READ_IR: STD_LOGIC_VECTOR(7 downto 0) := X"FB";
constant D12_COMMAND_SEL_EP0_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"00";
constant D12_COMMAND_SEL_EP0_IN: STD_LOGIC_VECTOR(7 downto 0) := X"01";
constant D12_COMMAND_SEL_EP1_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"02";
constant D12_COMMAND_SEL_EP1_IN: STD_LOGIC_VECTOR(7 downto 0) := X"03";
constant D12_COMMAND_SEL_EP2_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"04";
constant D12_COMMAND_SEL_EP2_IN: STD_LOGIC_VECTOR(7 downto 0) := X"05";
constant D12_COMMAND_READ_LTS_EP0_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"40";
constant D12_COMMAND_READ_LTS_EP0_IN: STD_LOGIC_VECTOR(7 downto 0) := X"41";
constant D12_COMMAND_READ_LTS_EP1_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"42";
constant D12_COMMAND_READ_LTS_EP1_IN: STD_LOGIC_VECTOR(7 downto 0) := X"43";
constant D12_COMMAND_READ_LTS_EP2_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"44";
constant D12_COMMAND_READ_LTS_EP2_IN: STD_LOGIC_VECTOR(7 downto 0) := X"45";
constant D12_COMMAND_RW_BUFFER: STD_LOGIC_VECTOR(7 downto 0) := X"F0"; 
constant D12_COMMAND_ACK_SETUP: STD_LOGIC_VECTOR(7 downto 0) := X"F0";
constant D12_COMMAND_CLEAR_EP_BUFFER: STD_LOGIC_VECTOR(7 downto 0) := X"F0";   
constant D12_COMMAND_ENABLE_BUFFER: STD_LOGIC_VECTOR(7 downto 0) := X"FA";  

-- D12 Configuration 
constant D12_DMA:STD_LOGIC_VECTOR(7 downto 0) := X"C0";
constant D12_MODE_CONFIG:STD_LOGIC_VECTOR(7 downto 0) := X"12";
constant D12_MODE_CLOCK_DIV:STD_LOGIC_VECTOR(7 downto 0) := X"43";

-- D12 Constants
constant D12_NOLAZYCLOCK: STD_LOGIC_VECTOR(7 downto 0) := X"02";
constant D12_CLOCKRUNNING: STD_LOGIC_VECTOR(7 downto 0) := X"04";
constant D12_INTERRUPTMODE: STD_LOGIC_VECTOR(7 downto 0) := X"08";
constant D12_SOFTCONNECT: STD_LOGIC_VECTOR(7 downto 0) := X"10";
constant D12_ENDP_NONISO: STD_LOGIC_VECTOR(7 downto 0) := X"00";
constant D12_ENDP_ISOOUT: STD_LOGIC_VECTOR(7 downto 0) := X"40";
constant D12_ENDP_ISOIN: STD_LOGIC_VECTOR(7 downto 0) := X"80";
constant D12_ENDP_ISOIO: STD_LOGIC_VECTOR(7 downto 0) := X"C0";

constant D12_CLOCK_12M: STD_LOGIC_VECTOR(7 downto 0) := X"03";
constant D12_CLOCK_4M: STD_LOGIC_VECTOR(7 downto 0) := X"0B";
constant D12_SETTOONE: STD_LOGIC_VECTOR(7 downto 0) := X"40";
constant D12_SOFONLY: STD_LOGIC_VECTOR(7 downto 0) := X"80";

constant D12_DMASINGLE: STD_LOGIC_VECTOR(7 downto 0) := X"00";
constant D12_BURST_4: STD_LOGIC_VECTOR(7 downto 0) := X"01";
constant D12_BURST_8: STD_LOGIC_VECTOR(7 downto 0) := X"02";
constant D12_BURST_16: STD_LOGIC_VECTOR(7 downto 0) := X"03";
constant D12_DMAENABLE: STD_LOGIC_VECTOR(7 downto 0) := X"04";
constant D12_DMA_INTOKEN: STD_LOGIC_VECTOR(7 downto 0) := X"08";
constant D12_AUTOLOAD: STD_LOGIC_VECTOR(7 downto 0) := X"10";
constant D12_NORMALPLUSSOF: STD_LOGIC_VECTOR(7 downto 0) := X"20";
constant D12_ENDP4INTENABLE: STD_LOGIC_VECTOR(7 downto 0) := X"40";
constant D12_ENDP5INTENABLE: STD_LOGIC_VECTOR(7 downto 0) := X"80";

constant D12_INT_ENDPOINT0_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"01";
constant D12_INT_ENDPOINT0_IN: STD_LOGIC_VECTOR(7 downto 0) := X"02";
constant D12_INT_ENDPOINT1_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"04";
constant D12_INT_ENDPOINT1_IN: STD_LOGIC_VECTOR(7 downto 0) := X"08";
constant D12_INT_ENDPOINT2_OUT: STD_LOGIC_VECTOR(7 downto 0) := X"10";
constant D12_INT_ENDPOINT2_IN: STD_LOGIC_VECTOR(7 downto 0) := X"20";
constant D12_INT_BUSRESET: STD_LOGIC_VECTOR(7 downto 0) := X"40";
constant D12_INT_SUSPENDCHANGE: STD_LOGIC_VECTOR(7 downto 0) := X"80";
constant D12_INT_EOT: STD_LOGIC_VECTOR(7 downto 0) := X"01";

constant D12_SETUPPACKET_BIT: INTEGER8 := 5;

constant D12_BUFFER0FULL: STD_LOGIC_VECTOR(7 downto 0) := X"20";
constant D12_BUFFER1FULL: STD_LOGIC_VECTOR(7 downto 0) := X"40";

constant D12_FULLEMPTY: STD_LOGIC_VECTOR(7 downto 0) := X"01";
constant D12_STALL: STD_LOGIC_VECTOR(7 downto 0) := X"02"; 

---------------------------------------------------------------------------------------------------
-- PDIUSBD12 Device Config Data
---------------------------------------------------------------------------------------------------
constant D12_CONNECT_DATA: REG8x8:=
(
	D12_COMMAND_SET_DMA,
	D12_DMA,
	D12_COMMAND_SET_MODE,
	D12_MODE_CONFIG,
	D12_MODE_CLOCK_DIV,
	others => X"00"
); 
constant D12_CONNECT_DATA_TYPE: REG8x1:=
( 
	D12_COMMAND,
	D12_DATA, 
	D12_COMMAND,
	D12_DATA, 
	D12_DATA,
	others => '0'
);	
constant D12_CONNECT_DATA_LENGTH: INTEGER8 := 5;  

constant D12_EP0_ACK_DATA: REG8x8:=
(
	D12_COMMAND_SEL_EP0_OUT,
	D12_COMMAND_ACK_SETUP,
	D12_COMMAND_CLEAR_EP_BUFFER,
	D12_COMMAND_SEL_EP0_IN,
	D12_COMMAND_ACK_SETUP,
	others => X"00"
); 
constant D12_EP0_ACK_DATA_LENGTH: INTEGER8 := 5;
constant ep0_ack_data: REG8x8 := D12_EP0_ACK_DATA;

-- functions & procedures

function GetInterruptHandler(ir_0: STD_LOGIC_VECTOR(7 downto 0); ir_1: STD_LOGIC)
return TRANSEIVER_STATE;

function GetCommandHandler(cmd: STD_LOGIC_VECTOR(7 downto 0))
return TRANSEIVER_STATE;

function GetDataLength(w_high: STD_LOGIC_VECTOR(7 downto 0); w_low: STD_LOGIC_VECTOR(7 downto 0))
return INTEGER8;


end PDIUSBD12_PACKAGE;
--}} End of automatically maintained section

package body PDIUSBD12_PACKAGE is

	-- functions & procedures	
	function GetInterruptHandler(ir_0: STD_LOGIC_VECTOR(7 downto 0); ir_1: STD_LOGIC)
	return TRANSEIVER_STATE is
	variable check: STD_LOGIC_VECTOR(7 downto 0); 
	variable return_state: TRANSEIVER_STATE;
	begin
		return_state:= TS_IDLE;
		
		check := ir_0 and D12_INT_ENDPOINT0_OUT;
		if check = D12_INT_ENDPOINT0_OUT then 
			return_state:= TS_EP0_RECEIVE;
		end if;
		
		check := ir_0 and D12_INT_ENDPOINT0_IN;
		if check = D12_INT_ENDPOINT0_IN then 
			return_state:= TS_EP0_TRANSMIT;
		end if;

		check := ir_0 and D12_INT_ENDPOINT2_OUT;
		if check = D12_INT_ENDPOINT2_OUT then 
			return_state:= TS_EP2_RECEIVE;
		end if;
		
		check := ir_0 and D12_INT_ENDPOINT2_IN;
		if check = D12_INT_ENDPOINT2_IN then 
			return_state:= TS_EP2_TRANSMIT;
		end if;

		check := ir_0 and D12_INT_ENDPOINT1_OUT;
		if check = D12_INT_ENDPOINT1_OUT then
			return_state := TS_IDLE;
		end if;

		check := ir_0 and D12_INT_ENDPOINT1_IN;
		if check = D12_INT_ENDPOINT1_IN then
			return_state := TS_IDLE;
		end if;

		check := ir_0 and D12_INT_BUSRESET;
		if check = D12_INT_BUSRESET then
			return_state := TS_BUSRESET;
		end if;

		check := ir_0 and D12_INT_SUSPENDCHANGE;
		if check = D12_INT_SUSPENDCHANGE then
			return_state := TS_SUSPENDCHANGE;
		end if;

		if ir_1 = '1' then
			return_state := TS_IDLE;
		end if;
		
		return return_state;
		
	end GetInterruptHandler;   
	
	function GetCommandHandler(cmd: STD_LOGIC_VECTOR(7 downto 0))
	return TRANSEIVER_STATE is
	variable check: STD_LOGIC_VECTOR(7 downto 0); 
	variable return_state: TRANSEIVER_STATE;
	begin
		return_state:= TS_IDLE;
		
		case cmd is
		when RH_SEND_DESCRIPTOR_1ST =>
			return_state := TS_SEND_DESCRIPTOR;--TS_SEND_DESCRIPTOR_1ST;
		when RH_SEND_DESCRIPTOR =>
			return_state := TS_SEND_DESCRIPTOR;
		when RH_SET_ADDRESS =>
			return_state := TS_SET_ADDRESS;
		when RH_SET_CONFIGURATION =>
			return_state := TS_SET_CONFIGURATION; 
		when RH_SEND_CONFIGURATION =>
			return_state := TS_GET_CONFIGURATION; 
		when RH_SEND_INTERFACE =>
			return_state := TS_GET_INTERFACE;
		when RH_SEND_STATUS =>
			return_state := TS_SEND_STATUS;
		when RH_CLEAR_FEATURE =>
			return_state := TS_CLEAR_FEATURE;
		when RH_SET_FEATURE =>
			return_state := TS_SET_FEATURE;
		when RH_SET_INTERFACE =>
			return_state := TS_SET_INTERFACE;
		when others =>
			NULL;
		end case;
			
		return return_state;
		
	end GetCommandHandler;   	
	
	function GetDataLength(w_high: STD_LOGIC_VECTOR(7 downto 0); w_low: STD_LOGIC_VECTOR(7 downto 0))
	return INTEGER8 is
	begin
		return conv_integer(w_high);
	end;

	
end PDIUSBD12_PACKAGE;
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