---------------------------------------------------------------------------------------------------
--
-- Title       : FrequencyDivider
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua (louxinghua99@mails.tsinghua.edu.cn)
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
--
---------------------------------------------------------------------------------------------------
--
-- File        : e:\Courses\ComputerHardwareInterface\USB_IF_DESIGN\USB_IF\src\FrequencyDivider.vhd
-- Generated   : Fri Apr 16 10:42:38 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
-- This module implements frequency division according to 'div_factor' attribute.
-- Written by Lou Xinghua  
--
---------------------------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {FrequencyDivider} architecture {FrequencyDivider}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.USB_PACKAGE.all;



entity FrequencyDivider is 
	generic( 
		div_factor : INTEGER8 := 0
	);
	port(					
		reset_n : in STD_LOGIC;	  
		clk_origin : in STD_LOGIC; 
		clk : out STD_LOGIC
	);
end FrequencyDivider;

--}} End of automatically maintained section

architecture FrequencyDivider of FrequencyDivider is	

-- Internal Signals					 
signal clk_tmp: STD_LOGIC;

begin

	-- enter your statements here --  
	
	-- signal connection
	clk <= clk_tmp;
	
	-- main process
	main_process: process( reset_n, clk_origin )
	variable count: INTEGER8;
	begin
		if reset_n = '0' then
			count := 0;
			clk_tmp <= '0';
		elsif rising_edge(clk_origin) then
			if count = div_factor then
				clk_tmp	<= not clk_tmp;	
				count := 0;
			else
				count := count+1;
			end if;
		end if;
	end process;

end FrequencyDivider;