?? io_map.h
字號(hào):
#define TMRA0_CMPLD1_COMPARATOR_LOAD_14_MASK 16U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_15_MASK 32U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_16_MASK 64U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_17_MASK 128U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_18_MASK 256U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_19_MASK 512U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_110_MASK 1024U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_111_MASK 2048U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_112_MASK 4096U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_113_MASK 8192U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_114_MASK 16384U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_115_MASK 32768U
#define TMRA0_CMPLD1_COMPARATOR_LOAD__10_MASK 1023U
#define TMRA0_CMPLD1_COMPARATOR_LOAD__10_BITNUM 0U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_1_10_MASK 64512U
#define TMRA0_CMPLD1_COMPARATOR_LOAD_1_10_BITNUM 10U
#define TMRA0_CMPLD1 *((volatile word *)0x0000F048)
/*** TMRA0_CMPLD2 - Timer A Channel 0 Comparator Load Register 2; 0x0000F049 ***/
union {
word Word;
} TMRA0_CMPLD2_STR;
#define TMRA0_CMPLD2_COMPARATOR_LOAD_20_MASK 1U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_21_MASK 2U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_22_MASK 4U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_23_MASK 8U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_24_MASK 16U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_25_MASK 32U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_26_MASK 64U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_27_MASK 128U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_28_MASK 256U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_29_MASK 512U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_210_MASK 1024U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_211_MASK 2048U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_212_MASK 4096U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_213_MASK 8192U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_214_MASK 16384U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_215_MASK 32768U
#define TMRA0_CMPLD2_COMPARATOR_LOAD__20_MASK 1023U
#define TMRA0_CMPLD2_COMPARATOR_LOAD__20_BITNUM 0U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_2_10_MASK 64512U
#define TMRA0_CMPLD2_COMPARATOR_LOAD_2_10_BITNUM 10U
#define TMRA0_CMPLD2 *((volatile word *)0x0000F049)
/*** TMRA0_COMSCR - Timer A Channel 0 Comparator Status and Control Register; 0x0000F04A ***/
union {
word Word;
} TMRA0_COMSCR_STR;
#define TMRA0_COMSCR_CL10_MASK 1U
#define TMRA0_COMSCR_CL11_MASK 2U
#define TMRA0_COMSCR_CL20_MASK 4U
#define TMRA0_COMSCR_CL21_MASK 8U
#define TMRA0_COMSCR_TCF1_MASK 16U
#define TMRA0_COMSCR_TCF2_MASK 32U
#define TMRA0_COMSCR_TCF1EN_MASK 64U
#define TMRA0_COMSCR_TCF2EN_MASK 128U
#define TMRA0_COMSCR_CL_10_MASK 3U
#define TMRA0_COMSCR_CL_10_BITNUM 0U
#define TMRA0_COMSCR_CL_20_MASK 12U
#define TMRA0_COMSCR_CL_20_BITNUM 2U
#define TMRA0_COMSCR_TCF_1_MASK 48U
#define TMRA0_COMSCR_TCF_1_BITNUM 4U
#define TMRA0_COMSCR *((volatile word *)0x0000F04A)
word Reserved0[5]; /* Reserved (unused) registers */
} TMRA0_PRPH;
/******************************************
*** Peripheral TMRA1
*******************************************/
typedef volatile struct {
/*** TMRA1_CMP1 - Timer A Channel 1 Compare Register #1; 0x0000F050 ***/
union {
word Word;
} TMRA1_CMP1_STR;
#define TMRA1_CMP1_COMPARISON_10_MASK 1U
#define TMRA1_CMP1_COMPARISON_11_MASK 2U
#define TMRA1_CMP1_COMPARISON_12_MASK 4U
#define TMRA1_CMP1_COMPARISON_13_MASK 8U
#define TMRA1_CMP1_COMPARISON_14_MASK 16U
#define TMRA1_CMP1_COMPARISON_15_MASK 32U
#define TMRA1_CMP1_COMPARISON_16_MASK 64U
#define TMRA1_CMP1_COMPARISON_17_MASK 128U
#define TMRA1_CMP1_COMPARISON_18_MASK 256U
#define TMRA1_CMP1_COMPARISON_19_MASK 512U
#define TMRA1_CMP1_COMPARISON_110_MASK 1024U
#define TMRA1_CMP1_COMPARISON_111_MASK 2048U
#define TMRA1_CMP1_COMPARISON_112_MASK 4096U
#define TMRA1_CMP1_COMPARISON_113_MASK 8192U
#define TMRA1_CMP1_COMPARISON_114_MASK 16384U
#define TMRA1_CMP1_COMPARISON_115_MASK 32768U
#define TMRA1_CMP1_COMPARISON__10_MASK 1023U
#define TMRA1_CMP1_COMPARISON__10_BITNUM 0U
#define TMRA1_CMP1_COMPARISON_1_10_MASK 64512U
#define TMRA1_CMP1_COMPARISON_1_10_BITNUM 10U
#define TMRA1_CMP1 *((volatile word *)0x0000F050)
/*** TMRA1_CMP2 - Timer A Channel 1 Compare Register #2; 0x0000F051 ***/
union {
word Word;
} TMRA1_CMP2_STR;
#define TMRA1_CMP2_COMPARISON_20_MASK 1U
#define TMRA1_CMP2_COMPARISON_21_MASK 2U
#define TMRA1_CMP2_COMPARISON_22_MASK 4U
#define TMRA1_CMP2_COMPARISON_23_MASK 8U
#define TMRA1_CMP2_COMPARISON_24_MASK 16U
#define TMRA1_CMP2_COMPARISON_25_MASK 32U
#define TMRA1_CMP2_COMPARISON_26_MASK 64U
#define TMRA1_CMP2_COMPARISON_27_MASK 128U
#define TMRA1_CMP2_COMPARISON_28_MASK 256U
#define TMRA1_CMP2_COMPARISON_29_MASK 512U
#define TMRA1_CMP2_COMPARISON_210_MASK 1024U
#define TMRA1_CMP2_COMPARISON_211_MASK 2048U
#define TMRA1_CMP2_COMPARISON_212_MASK 4096U
#define TMRA1_CMP2_COMPARISON_213_MASK 8192U
#define TMRA1_CMP2_COMPARISON_214_MASK 16384U
#define TMRA1_CMP2_COMPARISON_215_MASK 32768U
#define TMRA1_CMP2_COMPARISON__20_MASK 1023U
#define TMRA1_CMP2_COMPARISON__20_BITNUM 0U
#define TMRA1_CMP2_COMPARISON_2_10_MASK 64512U
#define TMRA1_CMP2_COMPARISON_2_10_BITNUM 10U
#define TMRA1_CMP2 *((volatile word *)0x0000F051)
/*** TMRA1_CAP - Timer A Channel 1 Capture Register; 0x0000F052 ***/
union {
word Word;
} TMRA1_CAP_STR;
#define TMRA1_CAP *((volatile word *)0x0000F052)
/*** TMRA1_LOAD - Timer A Channel 1 Load Register; 0x0000F053 ***/
union {
word Word;
} TMRA1_LOAD_STR;
#define TMRA1_LOAD_LOAD0_MASK 1U
#define TMRA1_LOAD_LOAD1_MASK 2U
#define TMRA1_LOAD_LOAD2_MASK 4U
#define TMRA1_LOAD_LOAD3_MASK 8U
#define TMRA1_LOAD_LOAD4_MASK 16U
#define TMRA1_LOAD_LOAD5_MASK 32U
#define TMRA1_LOAD_LOAD6_MASK 64U
#define TMRA1_LOAD_LOAD7_MASK 128U
#define TMRA1_LOAD_LOAD8_MASK 256U
#define TMRA1_LOAD_LOAD9_MASK 512U
#define TMRA1_LOAD_LOAD10_MASK 1024U
#define TMRA1_LOAD_LOAD11_MASK 2048U
#define TMRA1_LOAD_LOAD12_MASK 4096U
#define TMRA1_LOAD_LOAD13_MASK 8192U
#define TMRA1_LOAD_LOAD14_MASK 16384U
#define TMRA1_LOAD_LOAD15_MASK 32768U
#define TMRA1_LOAD *((volatile word *)0x0000F053)
/*** TMRA1_HOLD - Timer A Channel 1 Hold Register; 0x0000F054 ***/
union {
word Word;
} TMRA1_HOLD_STR;
#define TMRA1_HOLD_HOLD0_MASK 1U
#define TMRA1_HOLD_HOLD1_MASK 2U
#define TMRA1_HOLD_HOLD2_MASK 4U
#define TMRA1_HOLD_HOLD3_MASK 8U
#define TMRA1_HOLD_HOLD4_MASK 16U
#define TMRA1_HOLD_HOLD5_MASK 32U
#define TMRA1_HOLD_HOLD6_MASK 64U
#define TMRA1_HOLD_HOLD7_MASK 128U
#define TMRA1_HOLD_HOLD8_MASK 256U
#define TMRA1_HOLD_HOLD9_MASK 512U
#define TMRA1_HOLD_HOLD10_MASK 1024U
#define TMRA1_HOLD_HOLD11_MASK 2048U
#define TMRA1_HOLD_HOLD12_MASK 4096U
#define TMRA1_HOLD_HOLD13_MASK 8192U
#define TMRA1_HOLD_HOLD14_MASK 16384U
#define TMRA1_HOLD_HOLD15_MASK 32768U
#define TMRA1_HOLD *((volatile word *)0x0000F054)
/*** TMRA1_CNTR - Timer A Channel 1 Counter Register; 0x0000F055 ***/
union {
word Word;
} TMRA1_CNTR_STR;
#define TMRA1_CNTR *((volatile word *)0x0000F055)
/*** TMRA1_CTRL - Timer A Channel 1 Control Register; 0x0000F056 ***/
union {
word Word;
} TMRA1_CTRL_STR;
#define TMRA1_CTRL_OM0_MASK 1U
#define TMRA1_CTRL_OM1_MASK 2U
#define TMRA1_CTRL_OM2_MASK 4U
#define TMRA1_CTRL_Co_INIT_MASK 8U
#define TMRA1_CTRL_DIR_MASK 16U
#define TMRA1_CTRL_LENGTH_MASK 32U
#define TMRA1_CTRL_ONCE_MASK 64U
#define TMRA1_CTRL_SCS0_MASK 128U
#define TMRA1_CTRL_SCS1_MASK 256U
#define TMRA1_CTRL_PCS0_MASK 512U
#define TMRA1_CTRL_PCS1_MASK 1024U
#define TMRA1_CTRL_PCS2_MASK 2048U
#define TMRA1_CTRL_PCS3_MASK 4096U
#define TMRA1_CTRL_CM0_MASK 8192U
#define TMRA1_CTRL_CM1_MASK 16384U
#define TMRA1_CTRL_CM2_MASK 32768U
#define TMRA1_CTRL_OM_MASK 7U
#define TMRA1_CTRL_OM_BITNUM 0U
#define TMRA1_CTRL_SCS_MASK 384U
#define TMRA1_CTRL_SCS_BITNUM 7U
#define TMRA1_CTRL_PCS_MASK 7680U
#define TMRA1_CTRL_PCS_BITNUM 9U
#define TMRA1_CTRL_CM_MASK 57344U
#define TMRA1_CTRL_CM_BITNUM 13U
#define TMRA1_CTRL *((volatile word *)0x0000F056)
/*** TMRA1_SCR - Timer A Channel 1 Status and Control Register; 0x0000F057 ***/
union {
word Word;
} TMRA1_SCR_STR;
#define TMRA1_SCR_OEN_MASK 1U
#define TMRA1_SCR_OPS_MASK 2U
#define TMRA1_SCR_FORCE_MASK 4U
#define TMRA1_SCR_VAL_MASK 8U
#define TMRA1_SCR_EEOF_MASK 16U
#define TMRA1_SCR_MSTR_MASK 32U
#define TMRA1_SCR_Capture_Mode0_MASK 64U
#define TMRA1_SCR_Capture_Mode1_MASK 128U
#define TMRA1_SCR_INPUT_MASK 256U
#define TMRA1_SCR_IPS_MASK 512U
#define TMRA1_SCR_IEFIE_MASK 1024U
#define TMRA1_SCR_IEF_MASK 2048U
#define TMRA1_SCR_TOFIE_MASK 4096U
#define TMRA1_SCR_TOF_MASK 8192U
#define TMRA1_SCR_TCFIE_MASK 16384U
#define TMRA1_SCR_TCF_MASK 32768U
#define TMRA1_SCR_Capture_Mode_MASK 192U
#define TMRA1_SCR_Capture_Mode_BITNUM 6U
#define TMRA1_SCR *((volatile word *)0x0000F057)
/*** TMRA1_CMPLD1 - Timer A Channel 1 Comparator Load Register 1; 0x0000F058 ***/
union {
word Word;
} TMRA1_CMPLD1_STR;
#define TMRA1_CMPLD1_COMPARATOR_LOAD_10_MASK 1U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_11_MASK 2U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_12_MASK 4U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_13_MASK 8U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_14_MASK 16U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_15_MASK 32U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_16_MASK 64U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_17_MASK 128U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_18_MASK 256U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_19_MASK 512U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_110_MASK 1024U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_111_MASK 2048U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_112_MASK 4096U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_113_MASK 8192U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_114_MASK 16384U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_115_MASK 32768U
#define TMRA1_CMPLD1_COMPARATOR_LOAD__10_MASK 1023U
#define TMRA1_CMPLD1_COMPARATOR_LOAD__10_BITNUM 0U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_1_10_MASK 64512U
#define TMRA1_CMPLD1_COMPARATOR_LOAD_1_10_BITNUM 10U
#define TMRA1_CMPLD1 *((volatile word *)0x0000F058)
/*** TMRA1_CMPLD2 - Timer A Channel 1 Comparator Load Register 2; 0x0000F059 ***/
union {
word Word;
} TMRA1_CMPLD2_STR;
#define TMRA1_CMPLD2_COMPARATOR_LOAD_20_MASK 1U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_21_MASK 2U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_22_MASK 4U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_23_MASK 8U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_24_MASK 16U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_25_MASK 32U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_26_MASK 64U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_27_MASK 128U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_28_MASK 256U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_29_MASK 512U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_210_MASK 1024U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_211_MASK 2048U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_212_MASK 4096U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_213_MASK 8192U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_214_MASK 16384U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_215_MASK 32768U
#define TMRA1_CMPLD2_COMPARATOR_LOAD__20_MASK 1023U
#define TMRA1_CMPLD2_COMPARATOR_LOAD__20_BITNUM 0U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_2_10_MASK 64512U
#define TMRA1_CMPLD2_COMPARATOR_LOAD_2_10_BITNUM 10U
#define TMRA1_CMPLD2 *((volatile word *)0x0000F059)
/*** TMRA1_COMSCR - Timer A Channel 1 Comparator Status and Control Register; 0x0000F05A ***/
union {
word Word;
} TMRA1_COMSCR_STR;
#define TMRA1_COMSCR_CL10_MASK 1U
#define TMRA1_COMSCR_CL11_MASK 2U
#define TMRA1_COMSCR_CL20_MASK 4U
#define TMRA1_COMSCR_CL21_MASK 8U
#define TMRA1_COMSCR_TCF1_MASK 16U
#define TMRA1_COMSCR_TCF2_MASK 32U
#define TMRA1_COMSCR_TCF1EN_MASK 64U
#define TMRA1_COMSCR_TCF2EN_MASK 128U
#define TMRA1_COMSCR_CL_10_MASK 3U
#define TMRA1_COMSCR_CL_10_BITNUM 0U
#define TMRA1_COMSCR_CL_20_MASK 12U
#define TMRA1_COMSCR_CL_20_BITNUM 2U
#define TMRA1_COMSCR_TCF_1_MASK 48U
#define TMRA1_COMSCR_TCF_1_BITNUM 4U
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