//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  vga.h

Abstract:  Common VGA register defines

Notes:
--*/

#ifndef __VGA_H__
#define __VGA_H__

// Direct access IO mapped registers

#define reg_AR_ADDR         0x3C0   // Select AR0..14.  On Writes, sets 3C0[write]->ATR_DATA
#define reg_AR_DATA         0x3C1   // Read/Write AR0..14 On Writes, sets 3C0[write]->ATR_AD
#define reg_STATUS_0        0x3C2   // CRT Irq Pending
#define reg_SR_ADDR         0x3C4   // Select SR0..18
#define reg_SR_DATA         0x3C5   // Read/Write SR0..18
#define reg_DAC_AD_MK       0x3C6   // Pixel read mask (put FF here!)
#define reg_DAC_RD_AD       0x3C7   // Read index into palette (auto-incr)
#define reg_DAC_STS         0x3C7   // DAC status - checks palette state
#define reg_DAC_WR_AD       0x3C8   // Write index into palette (auto-incr)
#define reg_DAC_DATA        0x3C9   // Access palette entry (use 3 times)
#define reg_GR_ADDR         0x3CE   // Select GR0..8
#define reg_GR_DATA         0x3CF   // Access GR0..8
#define reg_AR_RESET        0x3BA   // Reset flip flop to set3CO[write]->ATR_AD
#define reg_CR_ADDR         0x3D4   // Select CR0..CR24
#define reg_CR_DATA         0x3D5   // Read/Write CR0..CR24
#define reg_STATUS_1        0x3DA   // VSync Status

#endif