/***************************************************************************************************
 * NXP ISP176x host controller interface header file
 *
 * (c) 2006 NXP B.V., All rights reserved. <usb.linux@nxp.com>
 * 
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * File Name:   pehci.h
 * 
 * Refering linux kernel version 2.6.9
 *
 * History:     
 *
 * Date                Author                  Comments
 * ----------------------------------------------------------------------------------------------------
 * May 16, 2003        krishan                  initial version
 * May 02 2007	       Prabhakar		ported to 2.6.20 with backward compatibility with 2.6.9  
 *                                                                              
 *******************************************************************************************************/

#ifndef __PEHCI_H__
#define __PEHCI_H__

#define DRIVER_AUTHOR 	"NXP Semiconductors"
#define DRIVER_DESC 	"ISP1761 Enhanced Host Controller (EHCI) Driver"

/*    bus related stuff */
#define __ACTIVE                0x01
#define __SLEEPY                0x02
#define __SUSPEND               0x04
#define __TRANSIENT             0x80

#define USB_STATE_HALT          0
#define USB_STATE_RUNNING       (__ACTIVE)
#define USB_STATE_READY         (__ACTIVE|__SLEEPY)
#define USB_STATE_QUIESCING     (__SUSPEND|__TRANSIENT|__ACTIVE)
#define USB_STATE_RESUMING      (__SUSPEND|__TRANSIENT)
#define USB_STATE_SUSPENDED     (__SUSPEND)

/* System flags  */
#define HCD_MEMORY              0x0001
#define HCD_USB2                0x0020
#define HCD_USB11               0x0010

#define HCD_IS_RUNNING(state) ((state) & __ACTIVE)
#define HCD_IS_SUSPENDED(state) ((state) & __SUSPEND)


/*---------------------------------------------------
 *    Host controller related 
 -----------------------------------------------------*/
#define CMD_RESET               (1<<1)          /* reset HC not bus */
#define CMD_RUN                 (1<<0)          /* start/stop HC */
#define STS_PCD                 (1<<2)          /* port change detect */
/* NOTE:  urb->transfer_flags expected to not use this bit !!! */
#define EHCI_STATE_UNLINK       0x8000          /* urb being unlinked */

/*  Bits definations for qha*/
/* Bits PID*/
#define SETUP_PID               (2)
#define OUT_PID                 (0)
#define IN_PID                  (1)

/* Bits MULTI*/
#define MULTI(x)                ((x)<< 29)      
#define XFER_PER_UFRAME(x)      (((x) >> 29) & 0x3)

/*Active, EP type and speed bits */
#define QHA_VALID               (1<<0)
#define QHA_ACTIVE              (1<<31)

/*1761 error bit maps*/
#define HC_SOF_INT              (1<< 0)
#define HC_MSEC_INT             (1 << 1)
#define HC_EOT_INT              (1 << 3)

#define HC_INTL_INT             (1 << 7)
#define HC_ATL_INT              (1 << 8)
#define HC_ISO_INT              (1 << 9)

/*PTD error codes*/
#define PTD_STATUS_HALTED       (1 << 30)
#define PTD_XACT_ERROR          (1 << 28)
#define PTD_BABBLE              (1 << 29)

/*ep types*/
#define EPTYPE_BULK             (2 << 12)
#define EPTYPE_CONTROL          (0 << 12)
#define EPTYPE_INT              (3 << 12)
#define EPTYPE_ISO              (1 << 12)

#define PHCI_QHA_LENGTH         32

/*LINUX269*/
#define usb_inc_dev_use         usb_get_dev
#define usb_dec_dev_use         usb_put_dev
#define usb_free_dev            usb_put_dev

/*1761 host controller periodic size*/
#define PTD_PERIODIC_SIZE       32
#define MAX_PERIODIC_SIZE       32

/*periodic list*/
struct _periodic_list{
    int  framenumber;
    struct list_head itd_head;
};
typedef struct _periodic_list periodic_list;


/*iso ptd*/
struct _isp1761_isoptd{
    u32   td_info1;
    u32   td_info2;
    u32   td_info3;
    u32   td_info4;
    u32   td_info5;
    u32   td_info6;
    u32   td_info7;
    u32   td_info8;
}__attribute__ ((aligned (32)));

typedef struct _isp1761_isoptd isp1761_isoptd;

struct _isp1761_qhint{
    u32   td_info1;
    u32   td_info2;
    u32   td_info3;
    u32   td_info4;
    u32   td_info5;
#define INT_UNDERRUN (1 << 2)
#define INT_BABBLE    (1 << 1)
#define INT_EXACT     (1 << 0)
    u32   td_info6;
    u32   td_info7;
    u32   td_info8;
}__attribute__ ((aligned (32)));

typedef struct _isp1761_qhint isp1761_qhint;


struct _isp1761_qha{
    u32   td_info1;   /* First 32 bit */
    u32   td_info2;   /* Second 32 bit */
    u32   td_info3;   /* third 32 bit */
    u32   td_info4;   /* fourth 32 bit */
    u32   reserved[4];  
};
typedef struct _isp1761_qha isp1761_qha, *pisp1761_qha;




/*this does not cover all interrupts in 1761 chip*/
typedef struct _ehci_regs {

    /*standard ehci registers*/
    u32                 command;
    u32                 usbinterrupt;
    u32                 usbstatus;
    u32                 hcsparams;
    u32                 frameindex;

    /*isp1761 interrupt specific registers*/
    u32                 hwmodecontrol;  
    u32                 interrupt;
    u32                 interruptenable;
    u32                 interruptthreshold;
    u32                 iso_irq_mask_or;
    u32                 int_irq_mask_or;
    u32                 atl_irq_mask_or;
    u32                 iso_irq_mask_and;
    u32                 int_irq_mask_and;
    u32                 atl_irq_mask_and;
    u32     buffer_status;

    /*isp 1761 initialization registers*/
    u32                 reset;
    u32                 configflag;
    u32                 ports[4];

    /*isp1761 transfer specific registers*/
    u32                 isotddonemap;
    u32                 inttddonemap;
    u32                 atltddonemap;
    u32                 isotdskipmap;
    u32                 inttdskipmap;
    u32                 atltdskipmap;
    u32                 isotdlastmap;
    u32                 inttdlastmap;
    u32                 atltdlastmap;
    u32                     scratch;

}ehci_regs, *pehci_regs;

struct ehci_qh {
    /* first part defined by EHCI spec */
    u32                 hw_next;         /* see EHCI 3.6.1 */
    u32                 hw_info1;        /* see EHCI 3.6.2 */

    u32                 hw_info2;        /* see EHCI 3.6.2 */
    u32                 hw_current;      /* qtd list - see EHCI 3.6.4 */

    /* qtd overlay (hardware parts of a struct ehci_qtd) */
    u32                 hw_qtd_next;
    u32                 hw_alt_next;
    u32                 hw_token;
    u32                 hw_buf [5];
    u32                 hw_buf_hi [5];

    /* the rest is HCD-private */
    dma_addr_t          qh_dma;         /* address of qh */
    struct list_head    qtd_list;       /* sw qtd list */
    struct ehci_qtd             *dummy;
    struct ehci_qh              *reclaim;       /* next to reclaim */

    atomic_t                    refcount;
    wait_queue_head_t   waitforcomplete;
    unsigned            stamp;

    u8                  qh_state;

    /* periodic schedule info */
    u8                  usecs;          /* intr bandwidth */
    u8                  gap_uf;         /* uframes split/csplit gap */
    u8                  c_usecs;        /* ... split completion bw */
    unsigned short              period;         /* polling interval */
    unsigned short              start;          /* where polling starts */
    u8                  datatoggle;     /*data toggle*/

    /*handling the ping stuffs*/
    u8                  ping;   /*ping bit*/

    /*qtd <-> ptd management*/

    u32         qtd_ptd_index;  /* Td-PTD map index for this ptd */
    u32             type;          /* endpoint type */

    /*iso stuffs*/
    int                 next_uframe; /*next uframe for this endpoint*/
    struct list_head    itd_list;   /*list of tds to this endpoint*/

    /*scheduling requirements for this endpoint*/
    u32                    ssplit;
    u32                 csplit;
};

/* urb private part for the driver. */
typedef struct {
    struct ehci_qh      *qh;
    u16                 length;         /* number of tds associated with this request */
    u16                 td_cnt;         /* number of tds already serviced */
    int                 state;          /* State machine state when URB is deleted  */
    int         timeout;        /* timeout for bulk transfers */
    wait_queue_head_t   wait;   /* wait State machine state when URB is deleted */
    /*FIX solve the full speed dying*/
    struct timer_list   urb_timer;
    struct ehci_qtd             *qtd[0]; /* list pointer to all corresponding TDs associated with this request */

} urb_priv_t;

/*
 * EHCI Specification 0.95 Section 3.6
 * QH: describes control/bulk/interrupt endpoints
 * See Fig 3-7 "Queue Head Structure Layout".
 *
 * These appear in both the async and (for interrupt) periodic schedules.
 */


/*Defination required for the ehci Queuehead */
#define QH_HEAD                 0x00008000
#define QH_STATE_LINKED         1               /* HC sees this */
#define QH_STATE_UNLINK         2               /* HC may still see this */
#define QH_STATE_IDLE           3               /* HC doesn't see this */
#define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
#define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
#define QH_STATE_TAKE_NEXT      8               /*take the new transfer from*/
#define NO_FRAME ((unsigned short)~0)           /* pick new start */


/*memory management structures*/
#define MEM_KV
#ifdef MEM_KV
typedef struct isp1761_mem_addr {
    u32 phy_addr;       /* Physical address of the memory */
    u32 virt_addr;      /* after ioremap() function call */
    u8  num_alloc;  /* In case n*smaller size is allocated then for clearing purpose */
    u32 blk_size;    /*block size*/
    u8  blk_num;    /* number of the block*/
    u8  used;       /*used/free*/
} isp1761_mem_addr_t;
#else 
typedef struct isp1761_mem_addr {
    void        *phy_addr;      /* Physical address of the memory */
    void     *virt_addr;        /* after ioremap() function call */
    __u8          usage; 
    __u32       blk_size;    /*block size*/
}isp1761_mem_addr_t;

#endif

struct ehci_itd {
    /* first part defined by EHCI spec */
    u32                 hw_next;           /* see EHCI 3.3.1 */
    u32                 hw_transaction [8]; /* see EHCI 3.3.2 */
#define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
#define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
#define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */