?? uart_pc_tx.v
字號:
/******************************************************************************* File: uart_tb.v* Version: V0.0* Author: minjingguo <jingguo.min@shhic.com>* Date: 20070814* Company: SHHIC Co., Ltd.******************************************************************************* Description:* ******************************************************************************** Version: V0.1* Modifier: name <email>* Date:* Description:******************************************************************************/
// *************************
// MODULE DEFINTION
//**************************
module uart_pc_tx
(
//INPUT
rst ,
clk16x ,
din ,
wr ,
parity_def,
//OUTPUT
tbre , //tbre=0 if tx is empty
sdo
);
// *************************
// INPUTS
// *************************
input rst ;
input clk16x ;
input [7:0] din ;
input wr ;
input parity_def ;
// *************************
// OUTPUTS
// *************************
output tbre ;
output sdo ;
// *************************
// INTERNAL SIGNALS
// *************************
reg [3:0] cnt_clk ;
reg [3:0] cnt_byte ;
reg tbre ;
reg [7:0] tbr ;
reg sdo ;
reg [7:0] tsr ;
reg parity ;
// *************************
// CODE
// *************************
always @(posedge clk16x or negedge rst)
begin
if (rst== 1'h0)
begin
cnt_clk <= #1 4'hf;
cnt_byte <= #1 4'hf;
end
else
begin
if (cnt_byte==4'hf)
begin
if (wr)
begin
cnt_clk <= #1 4'b0;
cnt_byte <= #1 4'b0;
end
end
else
begin
cnt_clk <= #1 cnt_clk+1;
if (cnt_clk==4'hf)
begin
if (cnt_byte==4'hb)
cnt_byte <= #1 4'hf;
else
cnt_byte <= #1 cnt_byte+1;
end
end
end
end
always @(posedge clk16x or negedge rst)
begin
if (rst== 1'h0)
begin
tbre <= #1 1'b0;
tbr <= #1 8'b0;
end
else
begin
if (wr)
begin
tbre <= #1 1'b1;
tbr <= #1 din;
end
else if (cnt_clk==4'hf && cnt_byte == 4'hb)
begin
tbre <= #1 1'b0;
end
end
end
always @(posedge clk16x or negedge rst)
begin
if (rst== 1'h0)
begin
sdo <= #1 1'b1;
parity <= #1 1'b1 ;
tsr <= #1 8'b0;
end
else if (cnt_clk==4'h7)
begin
if (cnt_byte == 4'h0)
begin
tsr <= #1 tbr;
sdo <= #1 1'b0;
parity <= #1 parity_def;
end
else if ((cnt_byte >= 4'h1) && (cnt_byte <= 4'h8))
begin
tsr <= #1 {tsr[6:0], 1'h0};
sdo <= #1 tsr[7] ;
parity <= #1 parity ^ tsr[7] ;
end
else if (cnt_byte == 4'h9)
begin
sdo <= #1 parity ;
end
else if (cnt_byte == 4'ha)
begin
sdo <= #1 1'b0 ;
end
else if (cnt_byte == 4'hb)
begin
sdo <= #1 1'b1 ;
parity <= #1 parity_def;
end
end
end
endmodule
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