/* * include/linux/serial.h * * Copyright (C) 1992 by Theodore Ts'o. *  * Redistribution of this file is permitted under the terms of the GNU  * Public License (GPL) *//* * This is our internal structure for each serial port's state. *  * Many fields are paralleled by the structure used by the serial_struct * structure. * * For definitions of the flags field, see tty.h */#ifndef _LINUX_SERIAL_H#define _LINUX_SERIAL_Hstruct async_struct {	int			baud_base;	int			port;	int			irq;	int			flags; 		/* defined in tty.h */	int			hub6;		/* HUB6 plus one */	int			type; 		/* UART type */	struct tty_struct 	*tty;	int			read_status_mask;	int			timeout;	int			xmit_fifo_size;	int			custom_divisor;	int			x_char;	/* xon/xoff characater */	int			close_delay;	int			IER; 	/* Interrupt Enable Register */	int			event;	int			line;	int			count;	    /* # of fd on device */	int			blocked_open; /* # of blocked opens */	long			session; /* Session of opening process */	long			pgrp; /* pgrp of opening process */	struct termios		normal_termios;	struct termios		callout_termios;	struct wait_queue	*open_wait;	struct wait_queue	*close_wait;	struct wait_queue	*xmit_wait;	struct async_struct	*next_port; /* For the linked list */	struct async_struct	*prev_port;};/* * Events are used to schedule things to happen at timer-interrupt * time, instead of at rs interrupt time. */#define RS_EVENT_READ_PROCESS	0#define RS_EVENT_WRITE_WAKEUP	1#define RS_EVENT_HANGUP		2#define RS_EVENT_BREAK		3#define RS_EVENT_OPEN_WAKEUP	4/* * These are the UART port assignments, expressed as offsets from the base * register.  These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */#define UART_TX		0	/* Out: Transmit buffer (DLAB=0) */#define UART_DLL	0	/* Out: Devisor Latch Low (DLAB=1) */#define UART_DLM	1	/* Out: Devisor Latch High (DLAB=1) */#define UART_IER	1	/* Out: Interrupt Enable Register */#define UART_IIR	2	/* In:  Interrupt ID Register */#define UART_FCR	2	/* Out: FIFO Control Register */#define UART_LCR	3	/* Out: Line Control Register */#define UART_MCR	4	/* Out: Modem Control Register */#define UART_LSR	5	/* In:  Line Status Register */#define UART_MSR	6	/* In:  Modem Status Register */#define UART_SCR	7	/* I/O: Scratch Register *//* * These are the definitions for the FIFO Control Register */#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 *//* * These are the definitions for the Line Control Register *  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */#define UART_LCR_DLAB	0x80	/* Devisor latch access bit */#define UART_LCR_SBC	0x40	/* Set break control */#define UART_LCR_SPAR	0x20	/* Stick parity (?) */#define UART_LCR_EPAR	0x10	/* Even paraity select */#define UART_LCR_PARITY	0x08	/* Parity Enable */#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits *//* * These are the definitions for the Line Status Register */#define UART_LSR_TEMT	0x40	/* Transmitter empty */#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */#define UART_LSR_BI	0x10	/* Break interrupt indicator */#define UART_LSR_FE	0x08	/* Frame error indicator */#define UART_LSR_PE	0x04	/* Parity error indicator */#define UART_LSR_OE	0x02	/* Overrun error indicator */#define UART_LSR_DR	0x01	/* Receiver data ready *//* * These are the definitions for the Interrupt Indentification Register */#define UART_IIR_NO_INT	0x01	/* No interrupts pending */#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */#define UART_IIR_MSI	0x00	/* Modem status interrupt */#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */#define UART_IIR_RDI	0x04	/* Receiver data interrupt */#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt *//* * These are the definitions for the Interrupt Enable Register */#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */#define UART_IER_RDI	0x01	/* Enable receiver data interrupt *//* * These are the definitions for the Modem Control Register */#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */#define UART_MCR_OUT2	0x08	/* Out2 complement */#define UART_MCR_OUT1	0x04	/* Out1 complement */#define UART_MCR_RTS	0x02	/* RTS complement */#define UART_MCR_DTR	0x01	/* DTR complement *//* * These are the definitions for the Modem Status Register */#define UART_MSR_DCD	0x80	/* Data Carrier Detect */#define UART_MSR_RI	0x40	/* Ring Indicator */#define UART_MSR_DSR	0x20	/* Data Set Ready */#define UART_MSR_CTS	0x10	/* Clear to Send */#define UART_MSR_DDCD	0x08	/* Delta DCD */#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */#define UART_MSR_DDSR	0x02	/* Delta DSR */#define UART_MSR_DCTS	0x01	/* Delta CTS */#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */#endif /* _LINUX_SERIAL_H */