/* * Copyright (C) 2002 Intel Corporation (yu.tang@intel.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA * */#ifndef BLOB_ARCH_MAINSTONE_H#define BLOB_ARCH_MAINSTONE_H/* Use FFUART *///#define USE_SERIAL1	1#define USE_SERIAL2	1#define TERMINAL_SPEED	baud_115200/* the base address were BLOB is loaded by the first stage loader */#define BLOB_ABS_BASE_ADDR	(0xa0300400)/* where do various parts live in RAM */#define BLOB_RAM_BASE		(0xa0200000)#define KERNEL_RAM_BASE		(0xa0008000)#define PARAM_RAM_BASE		(0xa0210000)#define RAMDISK_RAM_BASE	(0xa0500000)/* and where do they live in flash */#define BLOB_FLASH_BASE		(0x00000000)#define BLOB_FLASH_LEN		(256 * 1024)#define PARAM_FLASH_BASE	(BLOB_FLASH_BASE + BLOB_FLASH_LEN)#define PARAM_FLASH_LEN		(0) /* no parameters */#define KERNEL_FLASH_BASE	(PARAM_FLASH_BASE + PARAM_FLASH_LEN)#define KERNEL_FLASH_LEN	(2 * 1024 * 1024)#define LOAD_RAMDISK		0 /* load ramdisk into ram */#define RAMDISK_FLASH_BASE	(KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)#define RAMDISK_FLASH_LEN	(4 * 1024 * 1024)/* the position of the kernel boot parameters */#define BOOT_PARAMS		(0xa0000100)/* the size (in kbytes) to which the compressed ramdisk expands */#define RAMDISK_SIZE		(8 * 1024)/* GPIO settings */#undef GPSR0_VALUE#undef GPSR1_VALUE#undef GPSR2_VALUE#undef GPSR3_VALUE#undef GPDR0_VALUE#undef GPDR1_VALUE#undef GPDR2_VALUE#undef GPDR3_VALUE#undef GPCR0_VALUE#undef GPCR1_VALUE#undef GPCR2_VALUE#undef GPCR3_VALUE#undef GAFR0_L_VALUE#undef GAFR0_U_VALUE#undef GAFR1_L_VALUE#undef GAFR1_U_VALUE#undef GAFR2_L_VALUE#undef GAFR2_U_VALUE#undef GAFR3_L_VALUE#undef GAFR3_U_VALUE#define GPSR0_VALUE	0x00708800#define GPSR1_VALUE	0x03cf0002#define GPSR2_VALUE	0x0021FC00#define GPSR3_VALUE	0x00000000#define GPCR0_VALUE	0x00001000#define GPCR1_VALUE	0x00000000#define GPCR2_VALUE	0x00000000#define GPCR3_VALUE	0x00000000#define GPDR0_VALUE	0xC27B9C04#define GPDR1_VALUE	0x00EFAA83#define GPDR2_VALUE	0x0E23FC00#define GPDR3_VALUE	0x001E1F81#define GAFR0_L_VALUE	0x94F00000#define GAFR0_U_VALUE	0x015A859A#define GAFR1_L_VALUE	0x999A955A#define GAFR1_U_VALUE	0x0005A4AA#define GAFR2_L_VALUE	0x6AA00000#define GAFR2_U_VALUE	0x55A8041A#define GAFR3_L_VALUE	0x56AA955A#define GAFR3_U_VALUE	0x00000001/* Memory configuration */#define MDREFR_VALUE	0x00000018#define MDCNFG_VALUE	0x00000AC9#define MDMRS_VALUE	0x00000000/* * #define MSC0_VALUE	0x39F2A7A3 */#define MSC1_VALUE	0x0000A691#define MSC2_VALUE	0x0000B884/* TFTP download RAM base */#define TFTP_RAM_START	0xa1000000/* FPGA */#define MST_FPGA_BASE	0x08000000#define MST_LEDDAT1	__REG(MST_FPGA_BASE + 0x10)#define MST_LEDCTL	__REG(MST_FPGA_BASE + 0x40)#define MST_GPSWR	__REG(MST_FPGA_BASE + 0x60)#define MST_MSCWR1	__REG(MST_FPGA_BASE + 0x80)#define MST_MSCWR2	__REG(MST_FPGA_BASE + 0x84)/* USB client Soft-connect bit */#define MST_USBC_SC     (0x1<<4)/* LED */#define LED_ADDR	(MST_FPGA_BASE + 0x40)#define LED_ON		(0x00FE)#define LED_OFF		(0x00FF)/* SMC91c111 */#define SMC_BASE	(0x10000300)#endif