/*
***************************************************************************************************
* Copyright (C),2007
* Author        : YanZhongsan
* Email         : yanzhongsan@gmail.com
* Date          : 2007-10-17
* File name     : DS1302.h
* Description   : DS1302 driver head file
* Version       : V 1.0
* Others        : This file is the driver of DS1302
***************************************************************************************************
*/

#ifndef DS1302_H
#define DS1302_H

/****function description****/
void Init_DS1302(void);
UCHAR_8 DS1302ReadByte(UCHAR_8 addr);
void DS1302WriteByte(UCHAR_8 data,UCHAR_8 addr);

/****Define the DS1302's I/O port****/
// Define the DS1302's serial clock input line
// SCLK is used to synchronize data movement on the serial interface
#define DS_SCLK_PORT            PORTC
#define DS_SCLK_DDR             DDRC
#define DS_SCLK_PIN             PINC
#define DS_SCLK                 (1<<PC2)
#define SET_DS_SCLK_HIGH        DS_SCLK_PORT |= DS_SCLK
#define SET_DS_SCLK_LOW         DS_SCLK_PORT &= (~(DS_SCLK))

// Define the DS1302's data input and out line
// The data line is the bi-directional data pin for 3-wire serial interface
#define DS_DATA_PORT            PORTC
#define DS_DATA_DDR             DDRC
#define DS_DATA_PIN             PINC
#define DS_DATA                 (1u<<PC1)
#define DS_DATA_IS_HIGH         (0x00!=(DS_DATA_PIN & DS_DATA))
#define DS_DATA_IS_LOW          (0x00==(DS_DATA_PIN & DS_DATA))
#define SET_DS_DATA_HIGH        DS_DATA_PORT |= DS_DATA
#define SET_DS_DATA_LOW         DS_DATA_PORT &= (~(DS_DATA))
#define SET_DS_DATA_OUT         DS_DATA_DDR |= DS_DATA
#define SET_DS_DATA_IN          DS_DATA_DDR &= (~(DS_DATA))

// Define the DS1302's RESET line
// RESET wire must be assert high during read and writ data to DS1302
// All data transfers are initiated by driving the RST input high
// For data input,Data must be valid during the rising edge of the clock
// and data bit are output on the falling edge of clock
// If the RST signal is low all data transfer terminates and I/O pins goes
// to a high impedence state
// At power–up, RST must be a logic 0 until VCC > 2.0 volts. Also SCLK must be at
// a logic 0 when RST is driven to a logic 1 state
#define DS_RST_PORT             PORTC
#define DS_RST_DDR              DDRC
#define DS_RST_PIN              PINC
#define DS_RST                  (1<<PC0)
#define SET_DS_RST_HIGH         DS_RST_PORT |= DS_RST
#define SET_DS_RST_LOW          DS_RST_PORT &= (~(DS_RST))

#define DS_READ                 0x0001U
#define DS_WRITE                0x0000U

// Address of DS1302's clock
// The last bit(bit0) is the R/W control bit

// Bit7 is ch, Bit6 to bit4 are 10sec, Bit3 to bit0 are sec
// Bit7 of the seconds register is defined as the clock halt flag.When this bit is set to logic 1, the clock
// oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less
// than 100 nanoamps.When this bit is written to logic 0, the clock will start. The initial power on state is
// not defined.
#define DS_CLOCK_SEC            0x0080U//second

// Bit7 is always 0
// Bit6 to bit4 are 10min, Bit3 to bit0 are min
#define DS_CLOCK_MIN            0x0082U//minute

// Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour
// mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour
// mode, bit 5 is the second 10-hour bit (20 – 23 hours).
// Bit4 is the 10hour
#define DS_CLOCK_HOUR           0x0084U//hour

// Bit7 and bit6 always 0, Bit5 and bit4 are 10date, Bit3 to bit0 are date
#define DS_CLOCK_DATE           0x0086U//data

// Bit7 to bit5 always 0, Bit4 is 10month, Bit3 to bit0 are month
#define DS_CLOCK_MONTH          0x0088U//month

// Bit7 to bit3 always 0, Bit2 to bit0 are days(week)
#define DS_CLOCK_DAY            0x008AU//week

// Bit7 to bit4 are 10year, Bit3 to bit0 are year
#define DS_CLOCK_YEAR           0x008CU//year

// Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 – 6) are forced to 0 and
// will always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When
// high, the write protect bit prevents a write operation to any other register. The initial power on state is not
// defined. Therefore the WP bit should be cleared before attempting to write to the device.
#define DS_CLOCK_CONTL          0x008EU

#define DS_CLOCK_CHAR           0x0090U

#define DS_CLOCK_BURST          0x00BEU

// Address of DS1302's RAM
#define DS_RAM_ADDRESS0         0x00C0U
#define DS_RAM_ADDRESS1         0x00C2U
#define DS_RAM_ADDRESS2         0x00C4U
#define DS_RAM_ADDRESS3         0x00C6U
#define DS_RAM_ADDRESS4         0x00C8U
#define DS_RAM_ADDRESS5         0x00CAU
#define DS_RAM_ADDRESS6         0x00CCU
#define DS_RAM_ADDRESS7         0x00CEU
#define DS_RAM_ADDRESS8         0x00D0U
#define DS_RAM_ADDRESS9         0x00D2U
#define DS_RAM_ADDRESS10        0x00D4U
#define DS_RAM_ADDRESS11        0x00D6U
#define DS_RAM_ADDRESS12        0x00D8U
#define DS_RAM_ADDRESS13        0x00DAU
#define DS_RAM_ADDRESS14        0x00DCU
#define DS_RAM_ADDRESS15        0x00DEU
#define DS_RAM_ADDRESS16        0x00E0U
#define DS_RAM_ADDRESS17        0x00E2U
#define DS_RAM_ADDRESS18        0x00E4U
#define DS_RAM_ADDRESS19        0x00E6U
#define DS_RAM_ADDRESS20        0x00E8U
#define DS_RAM_ADDRESS21        0x00EAU
#define DS_RAM_ADDRESS22        0x00ECU
#define DS_RAM_ADDRESS23        0x00EEU
#define DS_RAM_ADDRESS24        0x00F0U
#define DS_RAM_ADDRESS25        0x00F2U
#define DS_RAM_ADDRESS26        0x00F4U
#define DS_RAM_ADDRESS27        0x00F6U
#define DS_RAM_ADDRESS28        0x00F8U
#define DS_RAM_ADDRESS29        0x00FAU
#define DS_RAM_ADDRESS30        0x00FCU

#define DS_RAM_BURST            0x00FFU

#endif